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quad - channel, 12 - bit, serial input, 4 ma to 20 ma and voltage outpu t dac with dynamic power control data sheet ad5735 rev. b information furnished by analog devices is believed to be ac curate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is gra nted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 C 2012 analog devices, inc. all rights reserved. features 12- bit resolution and monotonicity dynamic power control for thermal management current and voltage output pins connectable to a single terminal current output ranges: 0 ma to 20 ma, 4 ma to 20 ma, and 0 ma to 24 ma 0.1 % total unadjusted error ( tue) maximum voltage output ranges (with 20% overrange): 0 v to 5 v, 0 v to 10 v, 5 v, and 10 v 0.0 9 % total unadjusted error (tue) maximum user - programmable offset and gain on - chip diagnostics on - chip reference : 10 ppm/ c maximum ? 40c to +105c temperature range applications process control actuator control plcs general description the ad5735 is a quad - channel voltage and current output dac that operates with a power supply range from ? 26.4 v to +33 v . on - chip dynamic power control minimizes package power dissipation in current mode. this reduced power dissipation is achieved by regulating the voltage on the output driver from 7.4 v to 29.5 v using a dc - to - dc boost con verter optimized for minimum on - chip power dissipation. the ad5735 uses a versatile 3 - wire serial interface that operates at clock rates of up to 30 mhz and is compatible with standard spi, qspi?, microwire ? , dsp, and microcon troller interface standards. the serial interface also features optional crc - 8 packet error checking, as well as a watchdog timer that monitors activity on the interface. product highlights 1. dynamic p ower c ontrol for t hermal m anagement. 2. 1 2 - bit pe rformance. 3. quad c hannel. companion products product family: ad5755 , ad5755 - 1 , ad5757 , ad5737 external references: adr445 , adr02 digital isolators: adum1410 , adum1411 power: adp2302 , adp2303 additional companion products on the ad5735 product page functional block diagr am ad5735 av ss ?15v agnd av dd +15v av cc 5.0v dv dd dgnd ldac clear sclk sdin sync sdo fault dc-to-dc converter digital interface reference current and voltage output range scaling alert refout refin ad1 ad0 dac a sw x v boost_x gain reg a offset reg a r set_x +v sense_x ?v sense_x v out_x i out_x dac channel b dac channel a dac channel c dac channel d 7.4v to 29.5v + notes 1. x = a, b, c, or d. 09961-100 figure 1 .
ad5735 data sheet rev. b | page 2 of 48 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 produ ct highlights ........................................................................... 1 companion products ....................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 detailed functional block diagram .............................................. 3 specifications ..................................................................................... 4 ac performance characteristics ................................................ 7 timing characteristics ................................................................ 8 absolute maximum ratings .......................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configuration and function descriptions ........................... 12 typical performance characteristics ........................................... 15 voltage outputs .......................................................................... 15 current outputs ......................................................................... 19 dc - to - dc converter ................................................................. 23 reference ..................................................................................... 24 general ......................................................................................... 25 terminology .................................................................................... 26 theory of operation ...................................................................... 28 dac architecture ....................................................................... 28 power - on state of the ad5735 ................................................ 29 serial interface ............................................................................ 29 transfer function ....................................................................... 29 registers ........................................................................................... 30 enabling the output ................................................................... 31 data registers ............................................................................. 32 control registers ........................................................................ 34 readback operation .................................................................. 37 device features ............................................................................... 39 fault output ................................................................................ 39 voltage output short - circuit protection ................................ 39 digital offset and gain control ............................................... 39 status readback during a write .............................................. 39 asynchronous clear ................................................................... 40 packet error checking ............................................................... 40 watchdo g ti me r ......................................................................... 40 alert output ................................................................................ 40 internal reference ...................................................................... 40 external current setting resistor ............................................ 40 digital slew rate control .......................................................... 41 dynamic power control ............................................................ 41 dc - to - dc converters ............................................................... 42 ai cc supply requirements static .......................................... 43 ai cc supply requirements slewing ...................................... 43 applications informat ion .............................................................. 45 voltage and current output pins on the same terminal ..... 45 current output mode with internal r set ................................ 45 precision voltage reference selection ..................................... 45 driving inducti ve loads ............................................................ 46 transient voltage protection .................................................... 46 microprocessor interfacing ....................................................... 46 layout guidelines ....................................................................... 46 galvanically isolated interface ................................................. 47 outline dimensions ....................................................................... 48 ordering guide .......................................................................... 48 revision history 5 /12 rev. a to rev. b changes to figure 2 ........................................................................... 3 11/11 rev. 0 to rev. a added comments to output characteristics and accuracy, current output parameters in ta ble 1 ................................................................................................. 4 changes to power - on state of the ad5735 section .................. 29 changes to readback operation section .................................... 37 7/ 11 revision 0: initial version
data sheet ad5735 rev. b | page 3 of 48 detailed functional block diagram a d 5 7 3 5 a v s s ? 1 5 v a g n d a v d d +1 5 v a v c c 5 . 0 v d v d d d g n d l d a c c l ea r sc l k sd i n syn c sd o f a u l t d c -t o -d c c o n ver t er d yn a mi c po w er c o n t r o l i n pu t sh i f t r eg i st er a n d c o n t r o l st a t u s r eg i st er po w er -o n r eset r ef er en c e b u f f er s d a c r eg a d a c i n pu t d a t a r eg a v r e f w a t c h d o g t i mer (spi a c t i vi t y) v o u t r a n g e sc a l i n g a l er t r ef o u t r ef i n a d 1 a d 0 d a c a 1 2 1 2 sw a v b o o s t _ a g a i n r eg a o f f set r eg a r 1 r 2 r 3 r s e t _ a v o u t _ a i o u t _ b , i o u t _ c , i o u t _ d r s e t _ b , r s e t _ c , r s e t _ d v s e n s e _ b , v s e n s e _ c , v s e n s e _ d v o u t _ b , v o u t _ c , v o u t _ d i o u t _ a +v s e n s e _ a ? v s e n s e _ a d a c c h a n n el b d a c c h a n n el a d a c c h a n n el c d a c c h a n n el d sw b , sw c , sw d v b o o s t _ b , v b o o s t _ c , v b o o s t _ d 7 . 4 v t o 2 9 . 5 v v s e n 1 v s e n 2 + 0 9 9 6 1 - 0 0 1 3 0 k ? figure 2 .
ad5735 data sheet rev. b | page 4 of 48 specifications av dd = v boost_x = 15 v; av ss = ?15 v; dv dd = 2.7 v to 5.5 v; av cc = 4.5 v to 5.5 v; dc - to - dc converter disabled; agnd = dgnd = gndsw x = 0 v; refin = 5 v; voltage outputs: r l = 1 k?, c l = 220 pf; current outputs: r l = 300 ?; all specifications t min to t max , unless otherwise noted. table 1 . parameter 1 min typ max unit test conditions/comments voltage output output voltage ranges 0 5 v 0 10 v ?5 +5 v ?10 +10 v 0 6 v 0 12 v ?6 +6 v ?12 +12 v resolution 12 bits accuracy , volt age output total unadjusted error (tue) ?0.0 9 0.012 +0.09 % fsr 0 v to 5 v, 0 v to 10 v, 5 v, 10 v ranges ?0.13 0.05 +0.13 % fsr on overranges (0 v to 6 v, 0 v to 12 v, 6 v, 12 v) tue long - term stability 35 ppm fsr drift after 1000 hours, t j = 150c relative accuracy (inl) ?0.0 32 0.006 +0.0 32 % fsr differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic zero - scale error ?0.05 0.00 4 +0.0 5 % fsr 0 v to 5 v, 0 v to 10 v ranges ?0.08 0.004 +0.08 % fsr on over ranges (0 v to 6 v, 0 v to 12 v ) zero - scale tc 2 2 ppm fsr/c bipolar zero error ?0.0 5 0.00 3 +0.05 % fsr 5 v, 10 v ranges ?0.08 0.03 +0.08 % fsr on overranges (6 v, 12 v) bipolar zero tc 2 2 ppm fsr/c offset e rror ?0.065 0.00 5 +0.065 % fsr 0 v to 5 v, 0 v to 10 v, 5 v, 10 v ranges ?0.09 0.03 +0.09 % fsr on overranges (0 v to 6 v, 0 v to 12 v, 6 v, 12 v) offset tc 2 2 ppm fsr/c gain error ?0.08 0.004 +0.08 % fsr 0 v to 5 v, 0 v to 10 v, 5 v, 10 v ranges ?0.15 0.004 +0.15 % fsr on overranges (0 v to 6 v, 0 v to 12 v, 6 v, 12 v) gain tc 2 3 ppm fsr/c full - scale error ?0.09 0.0 1 +0.09 % fsr 0 v to 5 v, 0 v to 10 v, 5 v, 10 v ranges ?0.13 0.05 +0.13 % fsr on overranges (0 v to 6 v, 0 v to 12 v, 6 v, 12 v) full - scale tc 2 2 ppm fsr/c output characteristics , voltage output 2 headroom 1 2.2 v with respect to v boost supply footroom 1 1.4 v with respect to the av ss supply output voltage drift vs. time 20 ppm fsr drift after 1000 hours, ? scale output, t j = 150c, av ss = ?15 v short- cir cuit current 12/6 16/8 ma programmable by user; defaults to 16 ma typical resistive load 1 k? for specified performance capacitive load stability 10 nf 2 f external 220 pf compensation capacitor connected dc output impedance 0.06 ? dc psr r 50 v/v dc crosstalk 24 v current output output current ranges 0 24 ma 0 20 ma 4 20 ma resolution 12 bits
data sheet ad5735 rev. b | page 5 of 48 parameter 1 min typ max unit test conditions/comments accuracy, current output (external r set ) assumes ideal resistor , see exte rnal current setting resistor section for more information. total unadjusted error (tue) ?0.1 0.019 +0.1 % fsr tue long - term stability 100 ppm fsr drift after 1000 hours, t j = 150c relative accuracy (inl) ?0.032 0.006 +0.032 % fsr differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic offset error ?0.1 0.012 +0.1 % fsr o ffset error drift 2 4 ppm fsr/c gain error ?0.1 0.004 +0.1 % fsr gain tc 2 3 ppm fsr/c full - scale error ?0.1 0.014 +0.1 % fsr full - scale tc 2 5 ppm fsr/c dc crosstalk 0.0005 % fsr external r set accuracy, current output (internal r set ) total unadjusted error (tue) 3 , 4 ?0.14 0.022 +0.14 % fsr tue long - term stability 180 ppm fsr drift af ter 1000 hours, t j = 150c relative accuracy (inl) ?0.032 0.006 +0.032 % fsr differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic offset error 3 , 4 ?0.1 0.017 +0.1 % fsr offset error drift 2 6 ppm fsr/c gain error ?0.12 0.004 +0.12 % fsr gain tc 2 9 ppm fsr/c full - scale error 3 , 4 ?0.14 0.02 +0.14 % fsr full - scale tc 2 14 ppm fsr/c dc crosstalk 4 ?0.01 1 % fsr internal r set output characteristics, current output 2 current loop compliance voltage v boost_x ? 2.4 v boost_x ? 2.7 v output current drift vs. time drift after 1000 hours, ? scale output, t j = 150c 90 ppm fsr external r set 140 ppm fsr internal r set resistive load 1000 ? the dc -to- dc converter has been characterized with a maximum load of 1 k?, chosen such that compliance is not exceeded; see figure 51 and the dc - dc maxv bits in table 28 dc output impedance 100 m? dc psrr 0.02 1 a/v reference input/output reference input 2 refe rence input voltage 4.95 5 5.05 v for specified performance dc input impedance 45 150 m? reference output output voltage 4.995 5 5.005 v t a = 25c reference tc 2 ?10 5 +10 ppm/c output noise (0.1 hz to 10 hz) 2 7 v p -p noise spectral density 2 100 nv/hz at 10 khz output voltage drift vs. time 2 180 pp m drift after 1000 hours, t j = 150c capacitive load 2 1000 nf load current 9 ma see figure 62 short- circuit current 10 ma line regulation 2 3 ppm/v see figure 63 load regulation 2 95 ppm/ma see figure 62 thermal hysteresis 2 160 ppm first temperature cycle 5 ppm second temperature cycle
ad5735 data sheet rev. b | page 6 of 48 parameter 1 min typ max unit test conditions/comments dc - to - dc converter switch switch on resistance 0.425 ? switch leakage current 10 na peak current limit 0.8 a oscillat or oscillator frequency 11.5 13 14.5 mhz this oscillator is divided down to provide the dc -to- dc converter switching frequency maximum duty cycle 89.6 % at 410 khz dc -to- dc switching frequency digital inputs 2 jedec compliant input high voltage, v ih 2 v input low voltage, v il 0.8 v input current ?1 +1 a per pin pin capacitance 2.6 pf per pin digital outputs 2 sdo, alert pins output low voltage, v ol 0.4 v sinking 200 a output high voltage, v oh dv dd ? 0.5 v sourcing 200 a high i mpedance leakage current ?1 +1 a high impedance output capacitance 2.5 pf fault pin output low voltage, v ol 0.4 v 10 k? pull - up resistor to dv dd 0.6 v at 2.5 ma output high voltage, v oh 3.6 v 10 k? pull - up resistor to dv dd power requirements av dd 9 33 v av ss ?26.4 ?10.8 v dv dd 2.7 5.5 v av cc 4.5 5.5 v ai dd 8.6 10.5 ma voltage output mode on all channels, outputs unloaded, over supplies 7 7.5 ma current output mode on all channels ai ss ?11 ?8.8 ma voltage output mode on all channels, outputs unloaded, over supplies ?1.7 ma current output mode on all channels di cc 9.2 11 ma v ih = dv dd , v il = dgnd, internal oscillator running, over supplies ai cc 1 ma outputs unloaded, over supplies i boo st 5 2.7 ma per channel, voltage output mode, outputs unloaded, over supplies 1 ma per channel, current output mode power dissipation 173 mw av dd = 15 v, av ss = ?15 v, dc -to- dc converter enabled, current output mode, outputs disabled 1 temperature range: ?40c to +105c; typical at +25c. 2 guaranteed by design and characterization; not production tested. 3 for current outputs with internal r set , the offset, full - scale, and tue measurements exclude dc crosstalk. the measurements are made with all four channels enabled and loaded with the same code. 4 see the current output mode with internal r set section for more information about dc crosstalk. 5 efficiency plots in figure 53 through figure 56 include the i boost quiescent current.
data sheet ad5735 rev. b | page 7 of 48 ac perfor mance characteristic s av dd = v boost_x = 15 v; av ss = ?15 v; dv dd = 2.7 v to 5.5 v; av cc = 4.5 v to 5.5 v; dc - to - dc converter disabled; agnd = dgnd = gndsw x = 0 v; refin = 5 v; voltage outputs: r l = 2 k?, c l = 220 pf; current outputs: r l = 300 ?; all specif ications t min to t max , unless otherwise noted. table 2. parameter 1 min typ max unit test conditions/comments dynamic performance , voltage output output voltage settling time 11 s 5 v step to 0.03% fsr, 0 v to 5 v range 18 s 10 v step to 0.03% fsr, 0 v to 10 v range slew rate 1.9 v/s 0 v to 10 v range power - on glitch energy 150 nv - sec digital - to - analog glitch energy 6 nv - sec glitch impulse peak amplitude 25 mv digital feedthrough 1 nv - sec dac -to - dac crosstalk 2 nv - sec 0 v to 10 v range output noise (0.1 hz to 10 hz bandwidth) 0.01 lsb p -p 12- bit lsb, 0 v to 10 v range output noise spectral density 150 nv/hz measured at 10 khz, midscale output, 0 v to 10 v range ac psrr 83 db 200 mv , 5 0 hz/60 hz sine wave superimposed on power supply voltage dynamic performance, current output output current settling time 15 s to 0.1% fsr, 0 ma to 24 ma range see test conditions/comments ms for settling times when using the dc - to - dc con - vert er, see figure 47, figure 48 , and figure 49 output noise (0.1 hz to 10 hz bandwidth) 0.01 lsb p -p 12- bit lsb, 0 ma to 24 ma ra nge output noise spectral density 0.5 na/hz measured at 10 k hz, midscale output, 0 ma to 24 ma range 1 guaranteed by design and characterization; not production tested.
ad5735 data sheet rev. b | page 8 of 48 timing characteristi cs av dd = v boost_x = 15 v; av ss = ?15 v; dv dd = 2.7 v to 5.5 v; av cc = 4.5 v to 5.5 v; dc - to - dc converter disabled ; agnd = dgnd = gndsw x = 0 v; refin = 5 v; voltage outputs: r l = 1 k?, c l = 220 pf; current outputs: r l = 300 ?; all specifications t min to t max , unless otherwise noted. table 3. parameter 1, 2, 3 limit at t min , t max unit descripti on t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 13 ns min 24th/32nd sclk falling edge to sync rising edge (see figure 76 ) t 6 198 ns min sync high time t 7 5 ns min data setup time t 8 5 ns min data hold time t 9 20 s min sync rising edge to ldac falling edge (all dacs updated or any channel has digital slew rate control enabled) 5 s min sync rising edge to ldac falling edge (single dac updated) t 10 10 ns min ldac pulse wi dth low t 11 500 ns max ldac falling edge to dac output response time t 12 see table 2 s max dac output settling time t 13 10 ns min clear high time t 14 5 s max clear activation time t 15 40 ns max sclk r ising edge to sdo valid t 16 sync rising edge to dac output response time ( ldac = 0) 21 s min a ll dacs updated 5 s min single dac updated t 17 500 ns min ldac falling edge to sync rising edge t 18 800 ns min reset pulse width t 19 4 sync high to next sync low (digital slew rate control enabled) 20 s min all dacs updated 5 s min single dac updated 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with t rise = t fall = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.2 v. 3 see figure 3 , figure 4 , figure 5 , and figure 6 . 4 this specification applies if ldac is held low during the write cycl e; otherwise, see t 9 .
data sheet ad5735 rev. b | page 9 of 48 timing diagrams msb sclk sync sdin ldac ldac = 0 clear 1 2 24 lsb t 1 v out_x v out_x v out_x t 4 t 6 t 3 t 2 t 5 t 8 t 7 t 10 t 9 t 10 t 1 1 t 12 t 12 t 16 t 19 t 17 t 13 reset t 18 t 14 09961-002 figure 3 . serial interface timing diagram sync msb msb lsb lsb input word specifies register to be read nop condition t 6 t 15 sdin msb lsb undefined selected register data clocked out sdo sclk 24 24 1 1 09961-003 figure 4 . readback timing diagram
ad5735 data sheet rev. b | page 10 of 48 sdo disabled r/w sdin sclk sync sdo 1 2 16 lsb msb dut_ ad1 sdo_ enab dut_ ad0 x x x d15 d14 d1 d0 sta tus sta tus sta tus sta tus 09961-004 figure 5 . status readback during write , timing diagram 200 a i ol 200 a i oh v oh (min) or v ol (max) t o output pin c l 50pf 09961-005 figure 6 . load circuit for sdo timing diagram s
data sheet ad5735 rev. b | page 11 of 48 absolute maximum rat ings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr latch - up. table 4. parameter rating av dd , v b oost_x to agnd, dgnd ?0.3 v to +33 v av ss to agnd, dgnd +0.3 v to ?28 v av dd to av ss ?0.3 v to +60 v av cc to agnd ?0.3 v to +7 v dv dd to dgnd ?0.3 v to +7 v digital inputs to dgnd ?0.3 v to dv dd + 0.3 v or +7 v (whichever is less) digital outputs to dgnd ?0.3 v to dv dd + 0.3 v or +7 v (whichever is less) refin, refout to agnd ?0.3 v to av dd + 0.3 v or +7 v (whichever is less) v out_x to agnd av ss to v boost_x or 33 v if using the dc -to - dc c onverter + v sense_x , ? v sense_x to agnd av ss to v boost_x or 33 v if using the dc -to - dc converter i out_x to agnd av ss to v boost_x or 33 v if using the dc -to - dc converter sw x to agnd ?0.3 v to +33 v agnd, gndsw x to dgnd ?0.3 v to +0.3 v operating temperature range (t a ) industrial 1 ?40c to +105c storage temperat ure range ?65c to +150c junction temperature (t j max) 125c power dissipation ( t j max ? t a )/ ja lead temperature jedec industry standard soldering j - std -020 1 power dissipated on chip must be derated to keep the junction temperature below 125c. s tresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this s pecification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance junction - to - air thermal resist ance ( ja ) is specified for a jedec 4 - layer test board. table 5 . thermal resistance package type ja unit 64- lead lfcsp (cp -64-3) 20 c/w esd caution
ad5735 data sheet rev. b | page 12 of 48 pin configuration an d function descripti ons 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 poc reset av dd comp lv_a ?v sense_a +v sense_a comp dcdc_a v boost_a v out_a i out_a av ss comp lv_b ?v sense_b +v sense_b v out_b comp dcdc_b 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 r set_c r set_d refout refin comp lv_d ?v sense_d +v sense_d comp dcdc_d v boost_d v out_d i out_d av ss comp lv_c ?v sense_c +v sense_c v out_c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r set_b r set_a refgnd refgnd ad0 ad1 sync sclk sdin sdo dv dd dgnd ldac clear alert fault comp dcdc_c i out_c v boost_c av cc sw c gndsw c gndsw d sw d av ss sw a gndsw a gndsw b sw b agnd v boost_b i out_b 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad5735 top view (not to scale) pin 1 indicator notes 1.the exposed paddle should be connected to the potential of the av ss pin, or, alternatively, it can be left electrically unconnected. it is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. 09961-006 figure 7 . pin configuration table 6 . pin function descriptions pin no. mnemonic description 1 r set_b an external, precision, low drift , 15 k ? current setting resistor can be connected to this pin to improve the i out_b temperature drift performance. for more information, see the external current setting resistor section. 2 r set_a an external, precision, low drift , 15 k ? current setting resistor can be connected to this pin to improve the i out_a temperature drift performance. for more information, see the external current setting resistor section. 3 refgnd ground reference point for internal reference. 4 refgnd ground reference point for internal refer ence. 5 ad0 address decode for the device under test (dut) on the board. 6 ad1 address decode for the dut on the board. 7 sync frame synchronization signal for the serial interface. active l ow i nput. wh en sync is low, data is clocked into the input shift register on the falling edge of sclk. 8 sclk serial clock input. data is clocked into the input shift register on the falling edge of sclk. th e serial interface operates at clock speeds of up to 30 mhz. 9 s din serial data input. data must be valid on the falling edge of sclk. 10 sdo serial data output. used to clock data from the s erial register in readback mode (s ee figure 4 and figure 5 ). 11 dv dd digital supply pin . the voltage range is from 2.7 v to 5.5 v. 12 dgnd digital ground. 13 ldac load dac . this active low input is used to update the dac register and , consequently , the dac outputs. when ldac is tied permanently low, the addressed dac data register is updated on the rising edge of sync . if ldac is held high during the write cycle, the dac input register is updated, but the dac output is update d only on the falling edge of ldac (see figure 3 ). using this mode, all analog outputs can be updated simultaneously. the ldac pin must not be left unconnected. 14 clear active high, edge sensitive input. when this pin is asserted, the outpu t current and voltage are set to the programmed clear code bit setting. only channels enabled to be cleared are cleared . f or more information, s ee the asynchronous clear section. when clear is active, the dac output register cannot be written to.
data sheet ad5735 rev. b | page 13 of 48 pin no. mnemonic description 15 alert active high output. this pin is asserted when there is no spi activity on the interface pins for a pre set time. f or mo re information , see the alert output s ection . 16 fault active low , open - drain output. this pin is asserte d low when any of the following conditions is detected: open circuit in current mode ; short circuit in voltage mode ; pec error ; or an overtemperature condition (see the fault output section). 17 poc power - on condition. this pin d etermines the power - on condition and is read during power - on and after a device reset. if poc = 0, the device is powered up with the voltage and current channels in tristate mode. if poc = 1, the device is powered up with a 30 k? pull - down resistor to ground on the voltage output channel, and the current channel is in tristate mode. 18 reset hardware reset, active low input. 19 av dd positive analog supply pin . the voltage range is from 9 v to 33 v. 20 comp lv_a optional compensation capacitor connection for v out_a output buffer. connecting a 220 pf capacitor between this pin and the v out_a pin allows the voltage output to drive up to 2 f. note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. 21 ? v sense_a sense connection for the negative voltage output load connection for v out_a . this pin must stay within 3.0 v of agnd for specified operation. 22 + v sense_a sense connection for the positive voltage output load connection for v out_a . th e differen ce in voltage between th is pin and the v out_a pin is add ed directly to the headroom requirement. 23 comp dcdc_a dc -to -d c compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel a dc -to - dc converter. alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin . for more information, see the dc -to - dc converter compensation capacitors section and the ai cc supply requirements slewing section . 24 v boost_a supply for channel a current output stage (see figure 71 ). this pin is also the supply for the v out _a stage, which i s regulated to 15 v by the dc -to - dc converter. to use the dc -to - dc converter , connect this pin as shown in figure 77 . 25 v out_a buffered analog ou tput voltage for dac channel a. 26 i out_a current output pin for dac channel a. 27 av ss negative analog supply pin. the v oltage range is from ?10.8 v to ?26.4 v. 28 comp lv_b optional compensation capacitor connection for v out_b output buffer. connecting a 220 pf capacitor between this pin and the v out_b pin allows the voltage output to drive up to 2 f. note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. 29 ?v sense_b sense connection for the negative voltage output load connection for v out_b . this pin must stay within 3.0 v of agnd for specified operation. 30 + v sense_b sense connection for the positive voltage output load connection for v out_b . the difference in voltage between this pin and the v out_b pin is added directly to the headroom requirement. 31 v out_b buffered analog output voltage for dac channel b. 32 comp dcdc_b dc -to - dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel b dc -to - dc converter. alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin . for more information, see the dc -to - dc converter compensation capacitors section and the ai cc supply requirements slewing section . 33 i out_b current output pin for dac channel b. 34 v boost_b supply for channel b current output stage (see figure 71 ). this pin is also the supply for the v out_b stage, which is regulated to 15 v by the dc -to - dc converter. to use the dc -to - dc converter , connect this pin as shown in figure 77 . 35 agnd ground reference point for analog circuitry. this pin must be connected to 0 v. 36 sw b switching output for channel b dc -to - dc circuitry. to use the dc -to - dc converter , connect this pin as shown in figure 77 . 37 gndsw b ground connection for dc -to - dc switching circuit. this pin shoul d always be connected to ground. 38 gndsw a ground connection for dc -to - dc switching circuit. this pin should always be connected to ground. 39 sw a switching output for channel a dc - to - dc circuitry. to use the dc - to - dc converter, connect this pin as shown in figure 77 . 40 av ss negative analog supply pin. the voltage range is from ?10.8 v to ?26.4 v. 41 sw d switching output for channel d dc -to - dc circuitry. to use the dc -to - dc converter, connect this pin as shown in figure 77 . 42 gndsw d ground connec tion for dc -to - dc switching circuit. this pin should always be connected to ground. 43 gndsw c ground connection for dc -to - dc switching circuit. this pin should always be connected to ground. 44 sw c switching output for channel c dc -to - dc circuitry. to us e the dc -to - dc converter, connect this pin as shown in figure 77 .
ad5735 data sheet rev. b | page 14 of 48 pin no. mnemonic description 45 av cc supply for dc -to - dc circuitry. the voltage range is from 4.5 v to 5.5 v. 46 v boost_c supply for channel c current output stage (see figure 71 ). this pin is also the supply for the v out_c stage, which is regulated to 15 v by the dc -to - dc converter. to use the dc -to - dc converter, connect this pin as shown in figure 77 . 47 i out_c current output pin for dac channel c. 48 comp dcdc_c dc -to - dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel c dc -to - dc converter. alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin . for more information, see the dc -to - dc converter compensation capacitors section and the ai cc supply requirements slewing section . 49 v out_c buffered analog output voltage for dac channel c. 50 + v sense_c sense connection for the positive voltage output load connection for v out_c . the difference in voltage between this pin and the v out_ c pin is added directly to the headroom requirement. 51 ? v sense_c sense connection for the negative voltage output load connection for v out_c . this pin must stay within 3.0 v of agnd for specified operation. 52 comp lv_c optional compensation capacitor c onnection for v out_c output buffer. connecting a 220 pf capacitor between this pin and the v out_c pin allows the voltage output to drive up to 2 f. note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the set tling time. 53 av ss negative analog supply pin. the voltage range is from ?10.8 v to ?26.4 v. 54 i out_d current output pin for dac channel d. 55 v out_d buffered analog output voltage for dac channel d. 56 v boost_d supply for channel d current output stage (see figure 71 ). this pin is also the supply for the v out_d stage, which is regulated to 15 v by the dc -to - dc converter. to use the dc -to - dc converter, connect this pin as shown in figure 77 . 57 comp dcdc_d dc -to -dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel d dc - to - dc converter. alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to gr ound from this pin . for more information, see the dc -to - dc converter compensation capacitors section and the ai cc supply requirements slewing section . 58 +v sense_d sense connection for t he positive voltage output load connection for v out_d . the difference in voltage between this pin and the v out_d pin is added directly to the headroom requirement. 59 ? v sense_d sense connection for the negative voltage output load connection for v out_d . this pin must stay within 3.0 v of agnd for specified operation. 60 comp lv_d optional compensation capacitor connection for v out_d output buffer. connecting a 220 pf c apacitor between this pin and the v out_d pin allows the voltage output to drive up to 2 f. note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. 61 refin external reference voltage input. 62 refout internal reference voltage output. it is recommended that a 0.1 f capacitor be placed between refout and refgnd. 63 r set_d an external, precision, low drift , 15 k ? current setting resistor can be connected to this pin to improve the i out_d temperature drift performance. for more information, s ee the external current setting resistor section. 64 r set_c an external, pre cision, low drift , 15 k ? current setting resistor can be connected to this pin to improve the i out_c temperature drift performance. for more information, see the external current setting resistor section. epad e xposed pad. th e exposed paddle should be connected to the potential of the av ss pin, or, alternatively, it can be left electrically unconnected. it is recommended that the pad dle be thermally connected to a copper plane for enhanced thermal performance.
data sheet ad5735 rev. b | page 15 of 48 typical performance characteristics voltage outputs ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0 1000 2000 3000 4000 inl error (%fsr) code 10v range 12v range 10v range with dc-to-dc converter av dd = +15v av ss = ?15v t a = 25c 09961-208 figure 8. integral nonlinearity error vs. dac code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 1000 2000 3000 4000 dnl error (lsb) code 10v range 12v range av dd = +15v av ss = ?15v t a = 25c 09961-209 10v range with dc-to-dc converter figure 9. differential nonlinearity error vs. dac code ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 1000 2000 3000 4000 total unadjusted error (%fsr) code 10v range 12v range 10v range with dc-to-dc converter av dd = +15v av ss = ?15v t a = 25c 09961?210 figure 10. total unadjusted error vs. dac code ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 ?40 ?20 0 20 40 60 80 100 inl error (%fsr) temperature (c) av dd =+15v av ss = ?15v output unloaded +5v range max inl 10v range max inl 12v range max inl +5v range min inl 10v range min inl 12v range min inl 09961-211 figure 11. integral nonlinearity error vs. temperature ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?40 ?20 0 20 40 60 80 100 dnl error (lsb) temperature (c) max dnl min dnl 09961-212 av dd = +15v av ss = ?15v all ranges figure 12. differential nonlinearity error vs. temperature ?40 ?20 0 20 40 60 80 100 total unadjusted error (%fsr) temperature (c) 09961-129 ?0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 av dd = +15v av ss = ?15v output unloaded +5v range 10v range 12v range figure 13. total unadjusted error vs. temperature
ad5735 data sheet rev. b | page 16 of 48 ?40 ?20 0 20 40 60 80 100 full-scale error (%fsr) temper a ture (c) a v dd = +15v a v ss = ?15v output unloaded +5v range 10v range 12v range 09961-132 ?0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 figure 14 . full - scale error vs. temperature ?0.025 ?0.030 ?0.035 ?0.040 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 ?40 ?20 0 20 40 60 80 100 offset error (%fsr) temper a ture (c) a v dd = +15v a v ss = ?15v output unloaded 09961-133 +5v range 10v range 12v range figure 15 . offset error vs. temperature ?0.020 ?0.025 ?0.030 ?0.035 ?0.045 ?0.040 ?0.015 ?0.010 ?0.005 0 0.005 0.010 ?40 ?20 0 20 40 60 80 100 bipolar zero error (%fsr) temper a ture (c) 09961-134 a v dd = +15v a v ss = ?15v output unloaded 12v range 10v range figure 16 . bipolar zero error vs. temperature ?0.02 ?0.01 0 0.02 0.01 0.04 0.03 0.06 0.05 0.08 0.07 0.09 ?40 ?20 0 20 40 60 80 100 temper a ture (c) a v dd = +15v a v ss = ?15v output unloaded +5v range 10v range 12v range gain error (%fsr) 09961-135 f igure 17 . gain error vs. temperature 0 0.001 0.002 0.003 0.004 0.005 0.006 zero-scale error (%fsr) a v dd = +15v a v ss = ?15v output unloaded ?40 ?20 0 20 40 60 80 100 temper a ture (c) 09961-136 +6v range +5v range figure 18 . zero - scale error vs. temperature ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 5 10 15 20 25 30 in l error (%fsr) supp l y (v) t a = 25c 0 v t o 5 v r an g e a v ss = ?26.4v for a v dd > +26.4v a v ss = ?10.8v for a v dd < +10.8v m i n i n l m a x i n l 09961-219 figure 19 . integral nonlinearity error vs. supply
data sheet ad5735 rev. b | page 17 of 48 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 5 10 15 20 25 30 dnl error (lsb) supply (v) max dnl min dnl t a = 25c av ss = ?26.4v for av dd > +26.4v all ranges av ss = ?10.8v for av dd < +10.8v 09961-220 figure 20 . di fferential nonlinearity error vs. supply 0.020 0.015 0.010 0 ?0.010 ?0.020 0.005 ?0.005 ?0.015 ?0.025 5 10 15 20 25 30 t ot al unadjusted error (%fsr) supp l y (v) 0v t o 5v range t a = 25c a v ss = ?26.4v for a v dd > +26.4v a v ss = ?10.8v for a v dd < +10.8v 09961-035 max tue min tue figure 21 . total unadjusted error vs. supply 0.0020 0.0015 0.0010 0.0005 0 ?0.0005 ?0.0010 ?0.0015 ?0.0020 ?20 20 16 12 8 4 0 ?4 ?8 ?12 ?16 output vo lt age de lt a (v) output current (ma) 8m a limi t , code = 0xffff 16m a limi t , code = 0xffff a v dd = +15v a v ss = ?15v 10v range t a = 25c 09961-036 figure 22 . source and sink capability of the output amplifier 12 8 4 0 ?4 ?8 ?12 ?5 15 10 5 0 output vo lt age (v) time (s) a v dd = +15v a v ss = ?15v 10v range t a = 25c output unloaded 09961-037 figure 23 . full - scale positive step 12 8 4 0 ?4 ?8 ?12 ?5 15 10 5 0 output vo lt age (v) time (s) a v dd = +15v a v ss = ?15v 10v range t a = 25c output unloaded 09961-038 figure 24 . full - scale negative step 15 10 5 0 ?5 ?10 ?15 ?20 0 5 4 3 2 1 volt age (v) time (s) 0x7fff t o 0x8000 0x8000 t o 0x7fff a v dd = +15v a v ss = ?15v +10v range t a = 25oc 09961-039 figure 25 . digital - to - analog glitch
ad5735 data sheet rev. b | page 18 of 48 15 10 5 0 ?5 ?10 ?15 0 7 8 9 10 5 6 1 2 3 4 volt age (v) time (s) a v dd = +15v a v ss = ?15v 10v range t a = 25c output unloaded 09961-040 figure 26 . peak - to - peak noise (0.1 hz to 10 hz bandwidth) 300 200 100 0 ?100 ?200 ?300 0 7 8 9 10 5 6 1 2 3 4 time (s) a v dd = +15v a v ss = ?15v 10v range t a = 25c output unloaded 09961-041 volt age (v) figure 27 . peak - to - peak noise (100 khz bandwidth) 25 20 15 10 5 0 ?5 ?10 ?15 ?20 ?25 0 25 50 75 100 125 volt age (mv) time (s) a v dd = +15v a v ss = ?15v t a = 25c 09961-043 figure 28 . voltage vs. time on power - up 60 40 20 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 2 4 6 8 10 volt age (mv) time (s) poc = 1 poc = 0 a v dd = +15v a v ss = ?15v 10v range t a = 25c int_enable = 1 09961-044 figure 29 . voltage vs. time on output enable 0 ?120 ?100 ?80 ?60 ?40 ?20 10 100 1k 10k 100k 1m 10m v out_x psrr (db) frequenc y (hz) a v dd = +15v v boost = +15v a v ss = ?15v t a = 25c 09961-045 figure 30 . v out_x psrr vs. fr equency
data sheet ad5735 rev. b | page 19 of 48 current outputs ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0 1000 2000 3000 4000 in l error (%fsr) code av dd = + 15 v av ss = ? 15 v t a = 2 5c 4m a t o 20 m a, i n t er n al r set 4m a t o 20 m a, e xt er n al r set 4m a t o 20 m a, i n t er n al r set , w it h dc- t o-d c co n ve r t er 4m a t o 20 m a, e xt er n al r set , w it h d c- t o-dc c on v er t er 09961-231 figure 31 . integral nonlinearity error vs. dac code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 1000 2000 3000 4000 dn l error (lsb) code av dd = + 15 v av ss = ? 15 v t a = 2 5c 09961-232 4m a t o 20 m a, i n t er n al r set 4m a t o 20 m a, e xt er n al r set 4m a t o 20 m a, i n t er n al r set , w it h dc- t o-d c co n ve r t er 4m a t o 20 m a, e xt er n al r set , w it h d c- t o-dc c on v er t er figure 32 . differential nonlinearity error vs. dac code ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0 1000 2000 3000 4000 t ot al unadjusted error (%fsr) code av dd = + 15 v av ss = ? 15 v t a = 2 5c 09961-233 4m a t o 20 m a, i n t er n al r set 4m a t o 20 m a, interna l r set , w it h dc- t o- d c co n ver t er 4m a t o 20 m a, ex t er n al r set 4m a t o 20 m a, e xt er n al r set , w it h d c- t o-dc c on v er t er figure 33 . total unadjusted erro r vs. dac code ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 ?40 ?20 0 20 40 60 80 100 in l error (%fsr) temper a ture (c) 4 m a t o 2 0 m a r an g e m a x i n l 0 m a t o 2 0 m a r a n g e m a x i n l 0 m a t o 2 4 m a r an g e m a x i n l 4 m a t o 2 0 m a r a n g e m i n i n l 0 m a t o 2 0 m a r an g e m i n i n l 0 m a t o 2 4 m a r a n g e m i n i n l av dd = + 15 v av ss = ? 15 v/0v 09961-234 figure 34 . integral nonlinearity error vs. temperature, internal r set ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 ?40 ?20 0 20 40 60 80 100 in l error (%fsr) temper a ture (c) 4 m a t o 2 0 m a r an g e m a x i n l 0 m a t o 2 0 m a r a n g e m a x i n l 0 m a t o 2 4 m a r an g e m a x i n l 4 m a t o 2 0 m a r a n g e m i n i n l 0 m a t o 2 0 m a r an g e m i n i n l 0 m a t o 2 4 m a r a n g e m i n i n l av dd = + 15 v av ss = ? 15 v/0v 09961-235 figure 35 . integral nonlinearity error vs. temperature, external r set ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?40 ?20 0 20 40 60 80 100 dn l error (lsb) temper a ture (c) m a x dn l m i n dn l av dd = + 15 v av ss = ? 15 v/0v al l ranges interna l and externa l r set 09961-236 figure 36 . dif ferential nonlinearity error vs. temperature
ad5735 data sheet rev. b | page 20 of 48 ?0.025 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0.025 t ot al unadjusted error (%fsr) ?40 ?20 0 20 40 60 80 100 temper a ture (c) a v dd = +15v a v ss = ?15v 09961-155 4m a t o 20m a range, interna l r set 4m a t o 20m a range, externa l r set figure 37 . total unadjusted error vs. temperature ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 full-scale error (%fsr) ?40 ?20 0 20 40 60 80 100 temper a ture (c) 09961-157 a v dd = +15v a v ss = ?15v 4m a t o 20m a range, interna l r set 4m a t o 20m a range, externa l r set figure 38 . full - scale error vs. temperature ?0.025 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 gain error (%fsr) ?40 ?20 0 20 40 60 80 100 temper a ture (c) 09961-159 a v dd = +15v a v ss = ?15v 4m a t o 20m a range, interna l r set 4m a t o 20m a range, externa l r set figure 39 . gain error vs. temp erature ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 5 10 15 20 25 30 in l error (%fsr) supp l y (v) m i n i n l m a x i n l t a = 25c av ss = ?26.4v for av dd > +26.4v av ss = ?10.8v for av dd < +10.8v 09961-240 4m a t o 20m a range figure 40 . integral nonlinearity error vs. supply, external r set ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 5 10 15 20 25 30 in l error (%fsr) supp l y (v) m i n i n l m a x i n l 09961-241 t a = 25c av ss = ?26.4v for av dd > +26.4v av ss = ?10.8v for av dd < +10.8v 4m a t o 20m a range figure 41 . integral nonlinearity error vs. supply, internal r set ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 5 10 15 20 25 30 dnl error (lsb) supply (v) max dnl min dnl 09961-242 t a = 25c av ss = ?26.4v for av dd > +26.4v av ss = ?10.8v for av dd < +10.8v al l ranges figure 42 . differential nonline arity error vs. supply
data sheet ad5735 rev. b | page 21 of 48 ?0.005 ?0.010 ?0.015 ?0.020 ?0.025 ?0.030 ?0.035 0.005 0 10 5 15 20 25 30 t ot al unadjusted error (%fsr) supp l y (v) 4m a t o 20m a range t a = 25c a v ss = ?26.4v for a v dd > +26.4v a v ss = ?10.8v for a v dd < +10.8v 09961-060 max tue min tue figure 43 . total unadjusted error vs. supply , external r set t ot al unadjusted error (%fsr) 4m a t o 20m a range t a = 25c ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 09961-061 a v ss = ?26.4v for a v dd > +26.4v a v ss = ?10.8v for a v dd < +10.8v min tue 10 5 15 20 25 30 supp l y (v) max tue figure 44 . total unadjusted error vs. supply , internal r set 6 5 4 3 2 1 0 0 20 15 10 5 current (a) time (s) a v dd = +15v a v ss = ?15v t a = 25c r load = 300? 09961-062 figure 45 . current vs. tim e on power - up 4 ?10 ?8 ?6 ?4 ?2 0 2 0 1 2 3 4 5 6 current (a) time (s) a v dd = +15v a v ss = ?15v t a = 25c r load = 300? int_enable = 1 09961-063 figure 46 . current vs. time on output enable 0 5 10 15 20 25 30 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 time (ms) 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) a v cc = 5v t a = 25c i out_x v boost_x 09961-167 output current (ma) and v boost_x vo lt age (v) figure 47 . output current and v boost_x settling time with dc - to - dc converter (see figure 77 ) 0 5 10 15 20 25 30 output current (ma) ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 time (ms) t a = ?40c t a = +25c t a = +105c 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) a v cc = 5v 09961-168 figure 48 . output current settling time with dc - to - dc converter over temperature (see figure 77 )
ad5735 data sheet rev. b | page 22 of 48 0 5 10 15 20 25 30 output current (ma) ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 time (ms) a v cc = 4.5v a v cc = 5.0v a v cc = 5.5v 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 09961-169 figure 49 . output current settling time with dc - to - dc convert er over av cc (see figure 77) ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 0 2 4 6 8 10 12 14 current (ac-coupled) (a) time (s) a v cc = 5v f sw = 410khz induc t or = 10h (xal4040-103) 0m a t o 24m a range 1k? load externa l r set t a = 25c 20m a output 10m a output 09961-170 figure 50 . output current , ac - coupled vs. time with dc - to - dc converter (see figure 77 ) 8 7 6 5 4 3 2 1 0 0 5 10 15 20 headroom vo lt age (v) output current (ma) 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 09961-067 figure 51 . dc - to - dc converter headroom vs. output current (see figure 77 ) 0 ?120 ?100 ?80 ?60 ?40 ?20 10 100 1k 10k 100k 1m 10m i out_x psrr (db) frequenc y (hz) a v dd = +15v v boost_x = +15v a v ss = ?15v t a = 25c 09961-068 figure 52 . i out_x psrr vs. frequency
data sheet ad5735 rev. b | page 23 of 48 dc -to - dc converter 90 85 80 75 70 65 60 55 50 0 24 20 16 12 8 4 v boost_x efficienc y (%) output current (ma) 0m a t o 24m a range 1k? load externa l r set f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c a v cc = 4.5v a v cc = 5v a v cc = 5.5v 09961-016 figure 53 . effici ency at v boost_x vs. output current (see figure 77) 90 85 80 75 70 65 60 55 50 ?40 100 40 60 80 20 0 ?20 v boost_x efficienc y (%) temper a ture (c) 0m a t o 24m a range 1k? load externa l r set a v cc = 5v f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 20m a output 09961-017 figure 54 . efficiency at v boost_x vs. temperature (see figure 77 ) 80 70 60 50 40 30 20 0 24 20 16 12 8 4 i out_x efficienc y (%) output current (ma) 0m a t o 24m a range 1k? load externa l r set f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c a v cc = 4.5v a v cc = 5v a v cc = 5.5v 09961-018 figure 55 . output efficiency vs. output current (see figure 77 ) 80 70 60 50 40 30 20 ?40 100 40 60 80 20 0 ?20 i out_x efficienc y (%) temper a ture (c) 0m a t o 24m a range 1k? load externa l r set a v cc = 5v f sw = 410khz induc t or = 10h (xal4040-103) 20m a output 09961-019 figure 56 . output efficiency vs. temperature (see figure 77 ) 0 0.1 0.2 0.3 0.4 0.5 0.6 ?40 ?20 0 20 40 60 80 100 switch resis t ance (?) temper a ture (c) 09961-123 figure 57 . switch resistance vs. temperature
ad5735 data sheet rev. b | page 24 of 48 reference 16 14 12 10 8 6 4 2 0 ?2 0 0.2 0.4 0.6 0.8 1.0 1.2 volt age (v) time (ms) a v dd refout t a = 25c 09961-010 figure 58 . refout voltage turn - on transient 4 3 2 1 0 ?1 ?2 ?3 0 2 4 6 8 10 volt age (v) time (s) a v dd = 15v t a = 25c 09961-0 1 1 figure 59 . refout output noise (0.1 hz to 10 hz bandwidth) 150 100 50 0 ?50 ?100 ?150 0 5 10 15 20 time (ms) a v dd = 15v t a = 25c 09961-012 volt age (v) figure 60 . refout o utput noise (100 khz bandwidth) 5.0000 5.0005 5.0010 5.0015 5.0020 5.0025 5.0030 5.0035 5.0040 5.0045 5.0050 ?40 ?20 0 20 40 60 80 100 reference output vo lt age (v) temper a ture (c) 30 devices shown a v dd = 15v 09961-163 figure 61 . refout voltage vs. temperature (when the ad5735 is soldered onto a pcb, the reference shifts due to thermal shock on the package. the average output voltage shift is ?4 mv. measurement of these parts after seven days shows that the outputs typically shift back 2 mv toward their initial values. this second shift is due to the relaxation of stress incurred during soldering.) 5.002 5.001 5.000 4.999 4.998 4.997 4.996 4.995 0 2 4 6 8 10 reference output vo lt age (v) load current (ma) a v dd = 15v t a = 25c 09961-014 figure 62 . ref out voltage vs. load current 5.00000 4.99995 4.99990 4.99980 4.99985 4.99975 4.99970 4.99965 4.99960 10 15 20 25 30 reference output vo lt age (v) a v dd (v) t a = 25c 09961-015 figure 63 . refout voltage vs. av dd
data sheet ad5735 rev. b | page 25 of 48 general 450 400 350 300 250 200 150 100 50 0 0 1 2 3 4 5 di cc (a) sdin vo lt age (v) dv dd = 5v t a = 25c 09961-007 figure 64 . di cc vs. logic input voltage 10 8 6 4 2 0 ?12 ?10 ?8 ?6 ?4 ?2 10 15 20 25 30 current (ma) volt age (v) ai dd ai ss t a = 25c v out = 0v output unloaded 09961-008 figure 65 . supply current ( ai dd /ai ss ) vs. supply volta ge (av dd / |av ss | ) 8 7 0 1 2 3 4 5 6 current (ma) volt age (v) ai dd t a = 25c i out = 0m a 10 15 20 25 30 09961-009 figure 66 . supply current (ai dd ) vs. supply voltage (av dd ) 13.4 13.3 13.2 13.1 13.0 12.9 12.8 12.7 12.6 ?40 ?20 0 20 40 60 80 100 frequenc y (mhz) temper a ture (c) dv dd = 5.5v 09961-020 figure 67 . internal oscillator frequency vs. temperature 14.4 14.2 14.0 13.8 13.6 13.4 13.2 13.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 frequenc y (mhz) volt age (v) t a = 25c 09961-021 figure 68 . internal oscillator frequ ency vs. dv dd supply voltage
ad5735 data sheet rev. b | page 26 of 48 terminology relative accuracy or integral nonlinearity (inl) r elative accuracy, or integral nonlinearity (inl) , is a measure of the maximum deviation from the best fit line through the dac transfer function. inl is expres sed in percent of full - scale range (% fsr) . t ypical inl vs. code plot s are shown in figure 8 and figure 31. differential nonlinearity (dnl) differential nonlinearity (dnl) is the differen ce between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified dnl of 1 lsb maximum ensures monotonicity. the ad5735 is guaranteed monotonic by design. typical dnl vs. co de plot s are shown in figure 9 and figure 32. monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital input code. the ad5735 is monotonic over its full operating temperature range. negative full - scale error or zero - scale error negative full - scale error is the error in the dac output voltage when 0x0000 (straight binary coding) is loaded to the d ac register. zero - scale temperature coefficient ( tc ) zero - scale tc is a measure of the change in zero - scale error with a change in temperature. zero - scale tc is expressed in pp m fsr/c. bipolar zero error bipolar zero error is the deviation of the analog o utput from the ideal half - scale output of 0 v when the dac register is loaded with 0x8000 (straight binary coding). bipolar zero temperature coefficient (tc) bipolar zero tc is a measure of the change in the bipolar zero error with a change in temperature. it is expressed in ppm fsr/c. offset error in voltage output mode, offset error is the deviation of the analog output from the ideal quarter - scale output when the dac is configured for a bipolar output range and the dac register is loaded with 0x 4 000 (st raight binary coding). in current output mode, offset error is the deviation of the analog output from the ideal zero - scale output when all dac registers are loaded with 0x0000. offset error drift or offset tc offset error drift, or offset tc , is a measure of the change in offset error with changes in temperature and is expressed in ppm fsr/c. gain error gain error is a measure of the span er ror of the dac. it is the devia tion in slope of the dac transfer function from the ideal, expressed in % fsr . gain temperature coefficient (tc) gain tc is a measure of the change in gain err or with changes in temperature and is expressed in ppm fsr/c. full - scale error full - scale error is a measure of the output error when full - scale code is loaded to the dac register. ideally, the output should be full - scale ? 1 lsb. full - scale error is expressed in % fsr. full - scale temperature coefficient (tc) full - scale tc is a measure of the change in full - scale error with changes in temperature and is expressed in ppm fsr/c. tot a l unadjusted error (tue) total unadjusted error (tue) is a measure of the output error t hat includes all the error measurements: inl error, offset error, gain error, temperature, and t ime. tue is expressed in % fsr. dc crosstalk dc crosstalk is the dc chang e in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change on one dac while monitoring another dac, which is at midscale. current loop compliance voltage the c urrent l oop c ompliance v oltage is t he maximum voltage at the i out _x pin for which the output current is equal to the programmed value. voltage reference thermal hysteresis voltage reference thermal hysteresis is the difference in output voltage measured at +25c compared to th e output voltage measured at +25c after cycling the temperature from + 25c to ?40c to +105c and back to +25c. the hysteresis is specified for the first and second temperature cycles and is expressed in ppm. output voltage settling time output voltage settling time is the amount of time it takes for the output to settle t o a specified level for a full - scale input change. plots of settling time are shown in figure 23, figure 48, and figure 49. sle w rate the slew rate of a device is a limitation in the rate of change of the output voltage. the output slewing speed of a voltage output dac is usually limited by the slew rate of the amplifier used at its output. slew rate is measured from 10% to 90% of the output signal and is given in v/s. power - on glitch energy power - on glitch energy is the impulse injected into the analog output when the ad5735 is powered on. it is specified as the area of the glitch in nv - sec (s ee figure 28 and figure 45).
data sheet ad5735 rev. b | page 27 of 48 digital -to - analog glitch energy digital - to - analog glitch energy is the impulse injected into the analog output when the input c ode in the dac register changes state but the output voltage remains constant. it is normally specified as the area of the glitch in nv - sec and is measured when the digital input code is changed by 1 lsb at the major carry transition ( ~ 0x7fff to 0x8000). s ee figure 25. glitch impulse peak amplitude glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the dac register changes state. it is specified as the amplitude of the glitch in mv and is measured when the digital input code is changed by 1 lsb at the major carry transition (~0x7fff to 0x8000). see figure 25. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv - sec and measured with a full - scale code change on the data bus. dac -to - dac crosst alk dac - to - dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and a subsequent output change of another dac. dac - to - dac crosstalk includes both digital and analog crosstalk. it is measured by loading one d ac with a full - scale code change (all 0s to all 1s and vice versa) with ldac low while monitoring the output of another dac. the energy of the glitch is expressed in nv - sec. power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the power supply voltage. reference temperature coefficient (tc) reference tc is a measure of the change in the reference output voltage with change s in temperature. it is expressed in ppm/c. line regulation lin e regulation is the change in the reference output voltage due to a specified change in supply voltage. it is expressed in ppm/v. load regulation load regulation is the change in the reference output voltage due to a specified change in load current. it is expressed in ppm/ma. dc -to - dc converter headroom dc - to - dc c onverter h eadroom is the difference between the voltage required at the current output and the voltage supplied by the dc - to - dc converter (s ee figure 51) . output efficiency o utput efficiency is defined as the ratio of the power delivered to a channels load and the power delivered to the channels dc - to - dc input. the v boost_ x quiescent current is considered part of the dc - to - dc converters losses . cc cc load out ai av r i 2 efficiency at vboost_x the efficiency at v boost_ x is defined as the ratio of the power delivered to a channels v boost_x supply and the power delivered to the channels dc - to - dc input. the v boost_x quiescent current is considered part of th e dc - to - dc converters losses . cc cc x boost out ai av v i _
ad5735 data sheet rev. b | page 28 of 48 theory of operation the ad5735 is a quad, precision digital - to - current loop and voltage output converter designed to meet the requirements of industrial process control applications. it provides a high precision, fully integrated, low cost, single - chip solution for generating current loop and unipolar/bipolar voltage outputs. the current ranges available are 0 ma to 20 ma, 4 ma to 20 ma , and 0 ma to 24 m a . the voltage ranges available are 0 v to 5 v, 5 v, 0 v to 10 v, and 10 v. the current and voltage outputs are available on separate pins, and only one output is active at any one time. t he output configuration is user - selectable via the dac control reg ister. on - chip dynamic power control minimizes package power dissipation in current mode (see the dynamic power control section) . dac architecture the dac core architecture of the ad573 5 consists of two matched dac sections. a simplified circuit diagram is shown in figure 69 . the four msbs of the 12 - bit data - word are decoded to drive 15 switches, e1 to e15. each switch connects one of 15 match ed resistors either to ground or to the reference buffer output. the remaining eight bits of the data - word drive switch s0 to switch s7 of a n 8 - bit voltage mode r - 2r ladder network. 8-bit r-2r ladder four msbs decoded in t o 15 equa l segments 2r 2r s0 s1 s7 e1 e2 e15 v out 2r 2r 2r 2r 2r 09961-069 figure 69 . dac ladder structure the voltage ou tput from the dac core can be ? buffered and scaled to output a software selectable unipolar or bipolar voltage range (see figure 70 ) ? c onverted to a current, which is then mirrored to the supply rail so that the ap plication sees only a current source output (see figure 71 ) both the voltage and current outputs are supplied by v boost_x . the current and voltage are output on separate pins and cannot be output simultaneously. t he current and voltage output pins of a channel can be tied together (see the voltage and current output pins on the same terminal section) . range scaling 12-bit dac v out_x short f au l t +v sense_x ?v sense_x v out_x 09961-070 figure 70 . voltage output 12-bit dac v boost_x r2 t2 t1 r3 i out_x r set a1 a2 09961-071 figure 71 . voltage - to - current conversion circuitry voltage output amplifier the voltage output amplifier is capable of generating both unipolar and bipolar output voltages. it is capable of driving a load of 1 k? in parallel with 1 f (with an external compen - satio n capacitor) to agnd. the source and sink capabilities of the output amplifier are shown in figure 22 . the slew rate is 1.9 v/s with a full - scale settling time of 1 8 s max (10 v step). if remote sensing of the load is not required, connect +v sense_x directly to v out_x , and connect ?v sense _x directly to agnd . ? v sense_x must stay within 3.0 v of agnd for specified opera - tion. the difference in voltage between +v sense_x and v out_x should be added directly to the headroom requirement. driving large capacitive loads the volt age output amplifier is capable of driving capacitive loads of up to 2 f with the addition of a 220 pf , nonpolarized compensation capacitor on each channel. the 220 pf capacitor is connected between the comp lv_x pin and the v out_x pin. care should be tak en to choose an appropriate value of com - pensation capacitor. this capacitor, while allowing the ad5735 to drive higher capacitive loads and reduce overshoot, increases the settling time of the part and, theref ore, affects th e bandwidth of the system. with out the compensation capacitor, capacitive loads of up to 10 nf can be driven . reference buffers the ad5735 can operate with either an external or internal referenc e. the reference input requires a 5 v reference for specified performance. this input voltage is then buffered before it is applied to the dac.
data sheet ad5735 rev. b | page 29 of 48 power - on state of the ad5735 on initial power - up of the ad5735 , the state of the power - on reset circuit is dependent on the power - on condi tion (poc) pin. ? if poc = 0, both the voltage output and current output chan nels power up in tristate mode. ? if poc = 1, the voltage out put channel powers up with a 30 k? pull - down resistor to ground, and the current output channel powers up in tristate mode . t he output ranges are not enabled, but the default output range is 0 v to 5 v, and the clear code register is loaded with all 0s . therefore, if the user clears the part after power - up, the output is actively driven to 0 v if the channel has been enabled for clear. after device power on, or a device reset, it is recommended to wait 100 s or more before writing to the device to allow time for internal calibrations to take place. serial interface the ad5735 is controlled by a versatile 3 - wire serial interface that operates at clock rates of up to 30 mhz and is compatible with spi, qspi, microwire, and dsp standards. data co d ing is always straight binary. input shift register the input shift register is 24 bits wide. data is loaded into the device msb first as a 24 - bit word under the control of the serial clock input, sclk. data is clocked in on the falling edge of sclk. if pa cket error checking ( pec ) is enabled, an additional eight bits must be written to the ad5735 , creating a 32 - bit serial interface (see the packet error checking section) . t he dac output s can be updated in one of two ways : individual dac updating or simultaneous updating of all dacs. individual dac updating to update an individual dac , ldac is held low while data is clocked into the dac data register. the addressed dac output is updated on the rising edge of sync . see table 3 and figure 3 for timing information. simultaneous updating of all dacs to up d at e all dacs simultaneously , ldac is held high while data is clocked into the dac data register. after ldac is taken high, o nly the first write to the dac data register of each channel is valid ; s ubsequent writes to the dac data register are ignored , al though the se subsequent writes are returned if a readback is initiated . all dac outputs are updated by taking ldac low after sync is taken high. v out_x dac register inter f ace logic output amplifiers ldac sdo sdin 12-bit dac v refin sync dac d at a register offset and gain calibr a tion dac input register sclk 09961-072 figure 72 . simplified serial interface of the input loading circuitry for one dac channel transfer function table 7 shows the input code to ideal output voltage relationship for the ad5735 for straigh t binary data coding of the 10 v output range. table 7 . input code to ideal output voltage relationship digital input straight binary data coding analog output msb lsb 1 v out 1111 1111 1111 xx xx +2 v ref ( 20 47/ 20 48) 1111 1111 1110 xxxx +2 v ref ( 2046/ 2048) 1000 0000 0000 xxxx 0 v 0000 0000 0001 xxxx ?2 v ref ( 2047/ 2048) 0000 0000 0000 xxxx ?2 v ref 1 x = dont care.
ad5735 data sheet rev. b | page 30 of 48 registers table 8 , table 9 , and table 10 provide an overview of the registers for the ad5735 . table 8 . data registers for the ad5735 register description dac data registers the four dac data registers (one register per dac cha nnel) are u sed to write a dac code to each dac channel. the dac data bits are d15 to d4. gain registers the four gain registers (one register per dac channel) are used to program the gain trim on a per - c hannel basis. the gain data bits are d15 to d4. off set registers the four offset registers (one register per dac channel) are used to program the offset trim on a per - channel basis . the offset data bits are d15 to d4. clear code registers the four clear code registers (one register per dac channel) are us ed to program the clear code on a per - channel basis. the clear code data bits are d15 to d4. table 9. c ontrol registers for the ad5735 register description main control register the m ain control register is u sed to configure functions for the entire part. these functions include the following: enabling stat us readback during a write; enabling the output on all four dac channels simulta - neously; power - on of the dc -to - dc converter on all four dac channels simultaneously; and enabling and configuring the watchdog timer. f or more information , see the main control register section . dac control registers the four dac control registers (one register per dac channel) are used to configure the following functions on a per - channel basis: output range (for example, 4 ma to 20 ma or 0 v to 10 v); selection of the internal current sense resistor or an external current sense resistor; enabling/disabling the use of a clear co de; enabling/disabling overrange on a voltage channel; enabling/disabling the internal circuitry (dc -to - dc converter, dac, and internal amplifiers); power - on/power - off of the dc -to - dc converter; and enabling/ disabling the output channel. software registe r the software register is us ed to perform a reset , to toggle the user bit in the status register , and, as part of the watchdog timer feature, to verify correct data communication operation. dc -to - dc control register the dc -to - dc control register is used to set the control parameters for the dc -to - dc converter: maximum output voltage, phase, and switching frequency. this register is also used to select the internal compensa - tion resistor or an external compensation resistor for the dc -to - dc converter. sle w rate control registers the four slew rate control registers (one register per dac channel) are used to program the slew rate of the dac output. table 10 . readback register for the ad5 735 register description status register the status register contains any fault information, as well as a user toggle bit.
data sheet ad5735 rev. b | page 31 of 48 enabl ing the output to correctly write to and set up the part from a power - on conditi on, use the following sequence: 1. perform a hardware or softwar e reset after initial power - on. 2. configure the dc - to - dc converter supply block. set the dc - to - dc switching frequency, the maximum output voltage allowed, and the dc - to - dc converter phase between channels. 3. configure the dac control r eg ister on a per - channel basis. select t he output range, and enable the dc - to - dc converter block (dc_dc bit). other control bits can also be config - ured. set the int_enable bit , but do not set the outen (output enable) bit . 4. write the required code to the dac data register. this step implements a full internal dac calibration . for reduced output glitch, allow at least 200 s before performing step 5. 5. write to the dac control register again to enable the output (set the outen bit). figure 73 provides a flowchart of this sequence. power on. ste p 1: perform a software/hardware reset. ste p 4: ste p 2: write to dc-to-dc control register to set dc-to-dc clock frequency, phase, and maximum voltage. ste p 3: write to dac control register. select the dac channel and output range. set the dc_dc bit and other control bits as required. set the int_enable bit but do not set the outen bit. ste p 5: 09961-073 write to one or more dac data registers. write to dac control register. reload allow at least 200s between step 3 and step 5 for reduced output glitch. sequence as in step 3. set the outen bit to enable the output. figure 73 . programming sequence to correctly enable the output reprogramming the output range when changing the range of an output , the same sequence described in th e enabling the output section should be used. it is recommended that the range be set to 0 v (zero scale or midscale ) before the output is disabled . because the dc - to - dc switching frequency, maximum output voltag e, and phase have already been selected, there is no need to reprogram these values . figure 74 provides a flowchart of this sequence. ste p 3: write v alue t o the dac d at a register. ste p 1: write t o channe l ?s dac d at a register. set the output t o 0v (zero or midscale). ste p 2: write t o dac contro l register. set the new output range. kee p the dc_dc bit and the int_enable bit se t . ste p 4: write t o dac contro l register. reload sequence as in ste p 2. 09961-074 channe l output is enabled. disable the output (outen = 0) and set the outen bit t o enable the outpu t . figure 74 . programming sequence to change the output range
ad5735 data sheet rev. b | page 32 of 48 data registers the input shift register is 24 bits wide. when pec is enabled, the input shift register is 32 bits wide, with the last eight bits correspond ing to the pec code (see the packet error checking section for more information about pec). when writing to a data register, the format shown in table 11 must be used. dac data register when writing to a dac data register, bit d15 to bit d4 are the dac data bits . table 13 shows the register format, and tabl e 12 describes the function s of bit d23 to bit d16. table 11. input shift register for a write operation to a data register msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 to d0 r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 data table 12. descriptions of data register bits[d23:d16] bit name description r/ w this bit i ndicates whether the addressed register is written to or read from . 0 = write to the addressed register. 1 = read from the addressed register. dut_ad1, dut_ad0 used in association with the external pins ad1 and ad0, these bits determine wh ich ad5735 device is being addressed by the system controller. dut_ad1 dut_ad0 part addressed 0 0 pin ad1 = 0, pin ad0 = 0 0 1 pin ad1 = 0, pin ad0 = 1 1 0 pin ad1 = 1, pin ad0 = 0 1 1 pin ad1 = 1, pi n ad0 = 1 dreg2, dreg1, dreg0 these bits select the register to be written to. if a control register is selected (dreg[2:0] = 111) , the creg bits in the control register select the specific control register to be written to (see t able 20). dreg2 dreg1 dreg0 function 0 0 0 write to dac data register ( one dac channel ) 0 0 1 reserved 0 1 0 write to gain register (one dac channel ) 0 1 1 write to gain register s (all dac channels ) 1 0 0 write to offset register (one dac chan nel ) 1 0 1 write to offset register s (all dac channel s) 1 1 0 write to clear code register (one dac channel ) 1 1 1 write to a control register dac_ad1, dac_ad0 these bits are used to specify the dac channel. if a write to the part does not apply to a specific dac channel, these bits are dont care bits. dac_ad1 dac_ad0 dac channel 0 0 dac a 0 1 dac b 1 0 dac c 1 1 dac d table 13 . pr ogramming the dac data register d23 d22 d21 d20 d19 d18 d17 d16 d15 to d4 d3 to d0 r/ w dut_ad1 dut_ad0 0 0 0 dac_ad1 dac_ad0 dac data x 1 1 x = dont care.
data sheet ad5735 rev. b | page 33 of 48 gain register the 12 - bit gain register allows the user to adjust the gain of each channel in steps of 1 lsb . to write to the gain register of one dac cha nnel , set the dreg[2:0] bits to 010 (see table 14 ). t o write the same gain code to all four dac channels at the same time , set the dreg[2:0] bits to 011. the gain register coding is straight binary , as shown in table 15 . the default code in the gain register is 0xffff. t he maximum recommended gain trim is approximately 50% of the programmed range to maintain accuracy (for more information, s ee the digital offset and gain control section ) . offset register the 12 - bit offset register allows the user to adjust the offset of each channel by ? 2048 lsb to + 2047 lsb in steps of 1 lsb. to write to the offset register of one dac channel , set the dreg[2:0] bits to 100 (see tabl e 16 ) . t o write the same offset code to all four dac channels at the same tim e , set the dreg[2:0] bits to 101. the offset register coding is straight binary , as shown in table 17 . the default code in the offset register is 0x8000, which results in zero offset programmed to the output (for m ore infor - mation, s ee the digital offset and gain control section ) . clear code register the 12 - bit clear code register allows the user to set the clear value of each channel . to configure a channel to be cleared w hen the clear pin is activated, set the clr_en bit in the dac control register for that channel (see tabl e 24 ). to write to the clear code register, set the dreg[2:0] bits to 110 (see table 18 ). the default clear code is 0x0000 (for more informa - tion, s ee the asynchronous clear section ) . table 14 . programming the gain register r/ w du t_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 d15 to d4 d3 to d0 0 device address 0 1 0 dac channel address gain adjustment 1 111 table 15. gain register bit descriptions gain adjustment g15 g14 g13 to g5 g4 g3 to g0 +4096 lsb 1 1 111111111 1 1111 +4095 lsb 1 1 111111111 0 1111 1111 1 lsb 0 0 000000000 1 1111 0 lsb 0 0 000000000 0 1111 table 16. programming the offset register r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 da c_ad1 dac_ad0 d15 to d4 d3 to d0 0 device address 1 0 0 dac channel address offset adjustment 0000 table 17 . offset register bit descriptions offset adjustment of15 of14 of13 of12 to of5 of4 of3 to of0 + 2047 lsb 1 1 1 11111111 1 0000 + 2046 lsb 1 1 1 11111111 0 0000 0000 no adjustment (default) 1 0 0 00000000 0 0000 0000 ? 2047 lsb 0 0 0 00000000 1 0000 ? 2048 lsb 0 0 0 00000000 0 0000 table 18 . programming the clear code register r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 d15 to d4 d3 to d0 0 device address 1 1 0 dac channel address clear code 0000
ad5735 data sheet rev. b | page 34 of 48 control registers when writing to a control register, the format shown in table 19 must be used. see table 12 for information ab out the configura - tion of bit d23 to bit d16. the control registers are addressed by setting the dreg[2:0] bits (bits[d20:d18 ] in the input shift register) to 111 and then setting the creg[2:0] bits to select the specific control register (see table 20) . main control register the main control register options are shown in table 21 and table 22 . see the device features sect ion for more information about the features controlled by the main c ontrol r egister. table 19. input shift register for a write operation to a control register msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 to d0 r/ w dut_ad1 dut_ad0 1 1 1 dac_ad1 dac_ad0 creg2 creg1 creg0 data table 20. control register addresses (creg [ 2:0] bits ) creg2 (d15) creg1 (d14) creg0 (d13) control register 0 0 0 slew rate control regis ter (one per channel) 0 0 1 main control register 0 1 0 dac control register (one per channel) 0 1 1 dc -to -dc control register 1 0 0 software register table 21. programming the main control register d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 to d0 0 0 1 poc statread ewd wd1 wd0 x 1 shtcctlim outen_all dcdc_all x 1 1 x = dont care. table 22 . main control register bit descriptions bit name description poc the poc bit determines the state of the voltag e output channels during normal operation. poc = 0: t he output goes to the value set by the poc hardware pin when the voltage output is not enabled (default). poc = 1: t he output goes to the opposite value of the poc hardware pin when the voltage output is not enabled. statread enable status readback during a write. see the status readback during a write section. 0 = d isable status readback (default). 1 = enable status readback. ewd enable the watchdog timer. see the watchdog timer section. 0 = disable the watchdog timer (default). 1 = e nable the watchdog timer . wd1, wd0 timeout select bits. used to select the timeout period for the watchdog timer. wd1 wd0 timeout period (ms) 0 0 5 0 1 10 1 0 100 1 1 200 shtcctlim programmable short - circuit limit on the v out_x pin in the event of a short - circuit condition. 0 = 16 ma (default). 1 = 8 ma. outen_all setting this bit to 1 e nables the output on all four dacs simultaneously. do not use the outen_all bit when using the outen bit in the dac control register. dcdc_all setting this bit to 1 powers up the dc -to - dc converter on al l four channels simultaneously. to power down the dc -to - dc converters, all channel outputs must first be disabled. do not use t he dcdc_a ll bit when using the dc_dc bit in the dac control register.
data sheet ad5735 rev. b | page 35 of 48 dac control register the dac control register is used to configure each dac channel. the dac control register options are shown in table 23 and table 24. table 23 . programming the dac control register d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 x 1 x 1 x 1 x 1 int_enable clr_en outen rset dc_dc ovrng r2 r1 r0 1 x = dont care. table 24 . dac control register bit descriptions bit name description int_enable powers up the dc -to - dc converter, dac, and internal amplifiers for the selected channel. this bit applies to individual channels only ; it d oes not enable the ou tput. after setting this bit, i t is recommended that a >200 s delay be observed before enabling the output to reduce the output enable glitch. see figure 29 and figure 46 for plots of this glitch. clr_en per - channel clear enable bit. this bit s pecifies whether the selected channel is clear ed when the clear pin is activated. 0 = channel is not cleared when the part is cleared (default). 1 = c han nel is cleared when the part is cleared. outen enables or disables the selected output channel. 0 = channel disabled (default). 1 = c hannel enabled . rset selects the internal current sense resistor or an external current sense resisto r for the selected d ac channel. 0 = e xternal resistor selected (default). 1 = i nternal resistor selected . dc_dc powers up or powers down the dc -to - dc converter on the selected channel. all dc -to - dc converters can be powered up simultaneously using the dcdc_all bit in the mai n control register. to power down the dc -to - dc converter, the outen and int_enable bits must also be set to 0. 0 = dc -to - dc converter is powered down (default). 1 = dc -to - dc converter is powered up . ovrng enables 20% overrange on the voltage output channe l only. no current output overrange is available. 0 = overrange disabled (default). 1 = overrange enabled. r2, r1, r0 selects th e output range to be enabled. r2 r1 r0 output range selected 0 0 0 0 v to 5 v voltage range (default) 0 0 1 0 v to 10 v v oltage range 0 1 0 5 v voltage range 0 1 1 10 v voltage range 1 0 0 4 ma to 20 ma current range 1 0 1 0 ma to 20 ma current range 1 1 0 0 ma to 24 ma current range
ad5735 data sheet rev. b | page 36 of 48 software register the software register allows the user to perform a software reset of the part. this register is also used to set the user toggle bi t, d11, in the status register and as part of the watchdog timer f eature when that feature is enabled. bit d12 in the software register can be used to ensure that co mmunication has not been lost between the mcu and the ad5735 and that the datapath lines are working properly (that is, sdi n , sclk, and sync ). when the watchdog timer feature is enabled, the user must write 0x195 to bits[d11: d 0] of the software register within the timeout period. if this command is not received within the timeout period, the alert pin signals a fault condition. this command is only required when the watchdog timer feature is enabled. dc - to - dc control register the dc - to - dc control register allows the user to configure the dc - to - dc switching frequency and phase, as well as the maxi - mum allowable dc - to - dc output voltage. the dc - to - dc control register options are shown in table 27 and table 28. table 25 . programming the software register d15 d14 d13 d12 d11 to d0 1 0 0 user p rogram reset c ode/spi c ode table 26. software register bit descriptions bit name description user program this bit is mapped to bit d11 of the status register. when this bit is set to 1, bit d11 of the status register is set to 1. w hen this bit is set to 0, bit d11 of the status register is also set to 0 . this feature can be used to ensure that the spi pins are working correctly by writing a known bit value to this register and then reading back bit d11 from the status register. reset code/spi code option description res et code writing 0x555 to bits[d11:d0] performs a software reset of th e ad5735 . spi code if the watchdog timer feature is enabled, 0x195 must be written to the software register ( bits[d11:d0]) within the progr ammed timeout period (see table 22) . table 27. programming the dc -to - dc control register d15 d14 d13 d12 to d7 d6 d5 to d4 d3 to d2 d1 to d0 0 1 1 x 1 dc - dc c omp dc - dc p hase dc - dc f req dc - dc maxv 1 x = d ont care. table 28. dc -to - dc control register bit descriptions bit name description dc - dc comp selects the internal compensation resistor or an external compensation resistor for the dc -to - dc converter. see the dc -to - dc converter compensation capacitors section and the ai cc supply requirements slewing section . 0 = selects the internal 150 k? compensation resistor (default). 1 = bypasses the internal compensation resistor. when this bit is set to 1 , an external compensation resistor must be used; this resistor is placed at the comp dcdc_x pin in series with the 10 nf dc -to - dc compensation capacitor to ground. typically, a resistor of ~50 k? is recommended. dc - dc ph ase user - programmable dc -to - dc converter phase (between channels). 00 = all dc -to - dc converters clock on the same edge (default). 01 = channel a and channel b clock on the same edge; channel c and channel d clock on the opposite edge. 10 = channel a and ch annel c clock on the same edge ; channel b and channel d clock on the opposite edge. 11 = channel a, channel b, channel c, and channel d clock 90 out of phase from each other. dc - dc freq s witching frequency for the dc -to - dc converter ; this frequency is di vided down from the internal 13 mhz oscillator (see figure 67 and figure 68). 00 = 250 khz 10% . 01 = 410 khz 10% (default). 10 = 650 khz 10%. dc - dc maxv maximum al lowed v boost_x volt a ge supplied by the dc -to - dc converter. 00 = 23 v + 1 v/?1.5 v (default). 01 = 24.5 v 1 v. 10 = 27 v 1 v. 11 = 29.5 v 1 v.
data sheet ad5735 rev. b | page 37 of 48 slew rate control register this register is used to program the slew rate control for the selected dac channel. this feature is available on both the current and voltag e outputs. t he slew rate control is enabled/ d isabled and programmed on a per - channel basis. see table 29 and th e digital slew rate control section for more information. readback operation readback mode i s invoked by setting the r/ w bit = 1 in the serial input register write. see table 30 for the bits associated with a read - back operation. the dut_ad1 and dut_ad0 bits, in association with bi ts[rd 4: rd 0], select the register to be read (see table 31 ) . the remaining data bit s in the write sequence are don t care bits . during the next spi transfer, the data that appears on the sdo output contains the data from the previously addressed register (see figure 4 ) . this second spi transfer should be either a request to read another register on a third data transfer or a no operation command. the no operation command fo r dut a ddress 00 is 0x1ce000, for other dut addresses , bit d22 and bit d21 are set accordingly. readback example to read back the gain register of ad5735 device 1, channel a , implement the following sequence: 1. write 0xa80000 to the input register to configure device address 1 for read mode with the gain register of channel a selected. t he data bi ts, d15 to d0, are dont care bit s. 2. execute another read command or a no operation com - mand ( 0x3ce000 ). during this co mmand, the data from the channel a gain register is clocked out on the sdo line. table 29. programming the slew rate control register d15 d14 d13 d12 d11 to d7 d6 to d3 d2 to d0 0 0 0 s r e n x 1 sr_clock sr_step 1 x = dont care. table 30 . input shift register for a read operation msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 to d0 r/ w dut_ad1 dut_ad0 rd4 rd3 rd2 rd1 rd0 x 1 1 x = dont care. table 31. read address es (bits[rd4:rd0]) rd4 rd3 rd2 rd1 rd0 function 0 0 0 0 0 read dac a data register 0 0 0 0 1 read dac b data register 0 0 0 1 0 read dac c data register 0 0 0 1 1 read dac d data register 0 0 1 0 0 read dac a control register 0 0 1 0 1 r ead dac b control register 0 0 1 1 0 read dac c control register 0 0 1 1 1 read dac d control register 0 1 0 0 0 read dac a gain register 0 1 0 0 1 read dac b gain register 0 1 0 1 0 read dac c gain register 0 1 0 1 1 read dac d gain register 0 1 1 0 0 read dac a offset register 0 1 1 0 1 read dac b offset register 0 1 1 1 0 read dac c offset register 0 1 1 1 1 read dac d offset register 1 0 0 0 0 read dac a clear code register 1 0 0 0 1 read dac b clear code register 1 0 0 1 0 read dac c clear code register 1 0 0 1 1 read dac d clear code register 1 0 1 0 0 read d ac a slew rate control register 1 0 1 0 1 read dac b slew rate control register 1 0 1 1 0 read dac c slew rate control register 1 0 1 1 1 read dac d slew rate control register 1 1 0 0 0 read status register 1 1 0 0 1 read main control register 1 1 0 1 0 read dc - to - dc control register
ad5735 data sheet rev. b | page 38 of 48 status register the status register is a read - only register. this register contains any fault information , as a well as a ramp active bit (bit d 9 ) and a user toggle bit (bit d11) . when the statread bit in the main control register is set, the status register contents can be read back on the sdo pin during every write sequence. alterna - tively, if the statread bit is not set, the status register can be read using the normal readback operation (see the readback operation section) . table 32 . decoding the status register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dc - dcd dc - dcc dc - dcb dc - dca user t oggle pec e rror ramp a ctive over t emp v out_d f ault v out_c f ault v out_b f ault v out_a f ault i out_d f ault i out_c f ault i out_b f ault i out_a f ault table 33. status register bit descriptio ns bit name description dc - dcd in current output mode, this bit is set if the dc -to - dc converter on channel d cannot maintain compliance , for example, if the dc -to - dc converter is reaching its v max voltage ; i n this case, the i out_d fault bit is also set. see the dc -to - dc converter v max functionality section for more information about the operation of this bit under this condition. in voltage output mode, this bit is set if the dc -to - dc converter on channel d is unable to regulate to 15 v as expected. when this bit is set, it does not result in the fault pin going high. dc - dcc in current output mode, this bit is set if the dc -to - dc converter on channel c cannot maintain compliance, for example, if the dc -to - dc con verter is reaching its v max voltage ; i n this case, the i out_c fault bit is also set. see the dc -to - dc converter v max functionality section for more information about the operation of this bit under this condition. in voltage outpu t mode, this bit is set if the dc -to - dc converter on channel c is unable to regulate to 15 v as expected. when this bit is set, it does not result in the fault pin going high. dc - dcb in current output mode, this bit is set if the dc -to - dc converter on channel b cannot maintain compliance , for example, if the dc -to - dc converter is reaching its v max voltage ; i n this case, the i out_b fault bit is also set. see the dc -to - dc converter v max functionality section for m ore information about the operation of this bit under this condition. in voltage output mode, this bit is set if the dc -to - dc converter on channel b is unable to regulate to 15 v as expected. when this bit is set, it does not result in the fault pin going high. dc - dca in current output mode, this bit is set if the dc -to - dc converter on channel a cannot maintain compliance, for example, if the dc -to - dc converter is reaching its v max voltage ; i n this case, the i out_ a fault bit is also set. see the dc -to - dc converter v max functionality section for more information about the operation of this bit under this condition. in voltage output mode, this bit is set if the dc -to - dc converter on channel a is unable to regulate to 15 v as expected. when this bit is set, it does not result in the fault pin going high. user toggle user toggle bit. this bit is set or cl eared via the software register and can be used to verify data communications , if needed. pec error denotes a pec error on the last data - word received over the spi interface. ramp active this bit is set while any output channel is slewing ( digital slew rate control is enabled on at least one channel). over t emp this bit is set if the ad5735 core temperature exceeds approximately 150c. v out_d fault this bit is set if a fault is detected on the v out_d pin. v out_c fault this bit is set if a fault is detected on the v out_c pin. v out_b fault this bit i s set if a fault is detected on the v out_b pin. v out_a fault this bit is set if a fault is detected on the v out_a pin. i out_d fault this bit is set if a fault is detected on the i out_d pin. i out_c fault this bit is set if a fault is detected on the i out _c pin. i out_b fault this bit is set if a fault is detected on the i out_b pin. i out_a fault this bit is set if a fault is detected on the i out_a pin.
data sheet ad5735 rev. b | page 39 of 48 device features fault output the ad5735 is equipped wit h a fault pin, an active low , open - drain output that allows several ad5735 devices to be connected together to one pull - up resistor for global fault detection. the fault pin is forced active by any one of the following fault conditions : ? the voltage at i out_x attempts to rise above the compliance range due to an open - loop circuit or insufficient power supply voltage. the internal circuitry that develops the fault output avoids using a comparator with windowed limits because this requires an actual output error before the fault output becomes active. instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 v of remaining drive capability. thus, the fault output is activated slightly before the compliance limit is reached. ? a short circuit is detected on a voltage output pin. the short - circuit current is limited to 16 ma or 8 ma, which is prog rammable by the user. if the ad5735 i s used i n uni - polar supply mode, a short - circuit fault may be generated if the output voltage is below 50 mv. ? an interface error is detected due to a pec failure (s ee the packet error checking section). ? t he core temperature of the ad5735 exceeds approxi - mately 150c. the v out_x fault, i out_x fault, pec error, and over t emp bits of the s tatus register are used in conjunction with the fault output to inform the user which fault condition caused the fault output to be activated. voltage output short - circuit protection under normal operation, the voltage o utput sinks/sources up to 12 ma and maintains specified operation. the maximum output current or short - circuit current is programmable by the user and can be set to 16 ma or 8 ma. if a short circuit is detected, the fault pin goes low, and the relevant v out_x fault bit is set in the status register (see table 33) . digital offset and g ain control each dac channel has a gain (m) register and an offset (c) register, which allow trimming out of the gain and offset e rrors o f the entire signal chain. data from the dac data register is operated on by a digital multiplier and adder controlled by the contents of the gain and offset registers ; t he calibrated dac data is then st ored in the dac input register (see figure 75) . dac input register dac dac d at a register gain (m) register offset (c) register 09961-075 figure 75 . digita l offset and gain control although figure 75 indicates a multiplier and adder for each channel, the device has only one multiplier and one a dder, which are shared by all four channels. this design has impli - cations for the update speed when several channels are updated at once (see table 3 ). when data is written to the gain (m) or offset (c) register, the output is not automatically updated. instead, the next write to the dac channel uses the new gain and offset values to perform a new calibration and automatically updates the channel. the output data from the calibration is routed to the dac input reg ister. this data is then loaded to the dac , as described in the serial interface section. both the gain register and the offset register ha ve 12 bits of resolution. the correct order to calibrate the gain and offset is to first ca librate the gain and then calibrate the offset. the value (in decimal) that is written to the dac input register can be calculated as follows: 11 12 2 2 ) 1 ( ? + + = c m d code r dacregiste (1) where: d is the code loaded to the dac data register of the dac channel . m is the cod e in the gain register (default code = 2 1 2 ? 1). c is the code in the offset register (default code = 2 1 1 ). status readback duri ng a write the ad5735 can be configured to read back the contents of the status register during every write sequence. this f eature is enabled using the statread bit in the main control register. when this feature is enabled, the user can continuously monitor the status register and act quickly in the case of a fault. when status readback during a write is enabled, the contents of the 16 - bit status register (see table 33) are output on the sdo pin, as shown in figure 5 . w hen the ad5735 is power ed up , the status read back during a write feature is disabled . when this feature is enabled, readback of registers other than the status register is not available . to re a d back any other register, clear the statread bit before following the readback sequence (see the readback operation section) . the statread bit can be set high again after the register read.
ad5735 data sheet rev. b | page 40 of 48 asynchronous clear clear is an active high, edge sensitive input that allows the output to be cleared to a preprogrammed 1 2 - bit co de. this code is user - programmable via a per - channel 1 2 - bit clear code register. for a channel to be clear ed , set th e clr_en bit in the dac control register for that channel . if the clear function on a channel is not enabled, the outp ut remains in its curr ent state, independent of the level of the clear pin. when the clear signal return s low, the relevant outputs remain cleared u ntil a new value is programmed to them . packet error checkin g to verify that data has been received correctly in noisy environ - men ts, the ad5735 offers the option of packet error checking based on an 8 - bit cyclic redundancy check (crc - 8) . the device controlling the ad5735 should generate an 8 - bit frame check sequence using the following polynomial : c ( x ) = x 8 + x 2 + x 1 + 1 this value is added to the end of the data - word, and 32 bits are sent to the ad5735 before sync goes high. if the ad5735 sees a 32- bit frame, it performs the error check when sync goes high. if the error check is valid, the data is written to the selected register. if the error check fails, t he fault pin goes low and the pec error bit in the status register is set. after the status register is read , fault returns high (assuming that there are no other faults), and the pec error bit is cleared automatically. sdin sync sclk upd a te on sync high msb d23 lsb d0 24-bit d at a 24-bit d at a transfer?no error checking sdin f au l t sync sclk upd a te on sync high on l y if error check p assed f au l t pin goes low if error check f ails msb d31 lsb d8 d7 d0 24-bit d at a 8-bit crc 32-bit d at a transfer with error checking 09961-180 figure 76 . pec timing packet error checking can be used for transmi t t ing and receiv ing data packets. if status readback during a write is enabled, the pec values returned during the status readback operation should be ignored. i f status readback during a write is disabled, the user can still use the normal readback operation to monitor status register activity with pec. watchdog timer when enabled, an on - chip watchdog timer generates an alert signal if 0x195 is not written to the software register within the programmed timeout period. this feature is useful to ensure that communication has not been lost between the mcu and the ad5735 and that the datapath lines are working properly (th at is, sdi n , sclk, and sync ). if 0x195 is not received by the software register within the timeout period, the alert pin signals a fault condition. the alert pin is active high and can be connected directly to the clear pin to enable a clear in the event that comm unication from the mcu is lost. to enable t he watchdog timer and set the timeout period (5 ms, 10 ms, 100 ms, or 200 ms), program the main control register (see table 21 and table 22) . alert output the ad5735 is equipped with an alert pin. this pin is an active high cmos output. the ad5735 also has an internal watchdog timer. when enab led, the watchdog timer monitors spi communications. if 0x195 is not received by the software register within the timeout per iod, the alert pin is activated. internal reference the ad5735 contains an integrated 5 v voltage reference with initial accuracy of 5 mv maximum and a temperature coefficient of 10 ppm /c maximum. the reference voltage is buffered and is externally available for use elsewhere within the system. external current set ting resistor r set is an internal sense resistor that is part of the voltage - to - current conversion circuitry (see figure 71) . the stability of the output current value over temperature is dependent on the stability of the r set value . t o improve the stability of the output current over temperature, the internal r set resistor, r1, can be bypassed and an external , 15 k? , low drift resistor can be connected to the r set_x pin of the ad5735 . the external resistor is selected via the dac control register (see table 24). table 1 provides the performance specifications for the ad5735 with both the internal r set resistor and an external, 15 k? r set resistor. the use of an external r set resistor allows for improved performance over the internal r set resistor option. the external r set resistor specification s assume an ideal resistor; the actual performance depends on the absolute value and temperature coefficient of the resistor used. this directly affects the gain er ror of the output and, thus , the total unadjusted error. to arrive at the gain/tue error of the output with a specific external r set resistor, add the absolute error percentage of the r set resistor directly to the gain/tue err or of the ad5735 with the exter nal r set resistor, as shown in table 1 (expressed in % fsr).
data sheet ad5735 rev. b | page 41 of 48 digital slew rate co ntrol the digital slew rate control feature of the ad5735 allows the user to control the rate at which the output value changes. this feature is available on both the current and voltage outputs. with the slew rate control feature disabled, the output value changes at a rate limited by the outp ut drive circuitry and the attached load. to reduce the slew rate, the user can enabl e the digital slew rate control feature using the sren bit of the slew rate control register (see table 29). when slew rate contr ol is enabled, the output, instead of slewing directly between two values, steps digitally at a rate defined by the sr_clock and sr_step parameters . these parameters are accessible via the slew rate control register (see tabl e 29) . ? sr_clock defines the rate at which the digital slew is updated ; for example, i f the selected update rate is 8 khz, the output is u pdated every 125 s. ? sr_step defines by how much the output value changes at each update. together, these p arameters define the rate of change of the output value. table 34 and table 35 list the range of values for the sr_clock and sr_step parameters , respectively . table 34 . slew rate update clock options sr_clock update clock frequency 1 0000 64 k hz 0001 32 khz 0010 16 khz 0011 8 khz 0100 4 khz 0101 2 khz 0110 1 khz 0111 500 hz 1000 250 hz 1001 125 hz 1010 64 hz 1011 32 hz 1100 16 hz 1101 8 hz 1110 4 hz 1111 0.5 hz 1 these clock frequencies are divided down from the 13 mhz internal oscillator (s ee table 1 , figure 67 , and figure 68 ). table 35 . slew rate step size options sr_step step size ( lsb ) 000 1 001 2 010 4 011 16 100 32 101 64 110 128 111 256 the following equation describes the slew rate as a function of the step size, the update cl ock frequency, and the lsb size. size lsb frequency clock update size step change output rate slew = where: slew rat e is expressed in seconds. output change is expressed in amp ere s for i out_x or in volts for v out_x . the update clock frequency for any given value is the same for all output ranges. the step size, however, varies across output ranges for a given value of step size because the lsb size is different for each output range. when the slew rate control feature is enabled, all output changes occur at the programmed slew rate (see the dc - to - dc converter settling time section for more information). for example, if the clear pin is asserted, the output slews to the clear value at the programmed slew rate (assuming that the channel is enabled to be cleared). if more than one channel is enabled for digital slew rate control, care must be taken when asserting the clear pin. if a channel under slew rate control is slewing when the clear pin is asserted, other channels under slew rate control may cha nge directly to their clear code not under slew rate control. dynamic power c ontrol when configured in current output mode, the ad5735 provides integrated dynamic power control using a dc - to - dc boost converter circuit. this circuit reduces power consumption compared with standard designs. in standard current input module designs, the load resistor values can range from typically 50 ? to 750 ?. output module systems must source enough voltage to meet the complian ce voltage requirement across the full range of load resistor values. for example, in a 4 ma to 20 ma loop when driving 20 ma, a compliance voltage of >15 v is required. when driving 20 ma into a 50 ? load, a compliance voltage of only 1 v is required. th e ad5735 circuitry senses the output voltage and regulates this voltage to meet the compliance requirements plus a small headroom voltage. the ad5735 is capable of driving up to 24 ma through a 1 k? load.
ad5735 data sheet rev. b | page 42 of 48 dc -to - dc converters the ad5735 contains four independent dc - to - dc converters. these are used to provide dynamic control of the v boost _x supply voltage for each cha nnel (see figure 71 ). figure 77 shows the discre te components needed for the dc - to - dc circuitry, and the following sections describe component selection and operation of this circuitry. a v cc l dcdc d dcdc c dcdc 4.7f c fi l ter 0.1f r fi l ter c in sw x v boost_x 10f 10? 10h 09961-077 figure 77 . dc - to - dc circuit table 36 . recommended components for a dc - to - dc converter symbol component value manufacturer l dcdc xal4040 -103 10 h coilcraft ? c dcdc grm32er71h475ka88l 4.7 f murata d dcdc pmeg3010bea 0.285 v f nxp it is recommended that a 10 ?, 100 nf low - pass rc filter be placed after c dcdc . this filter consumes a small amount of power but reduces the amount of ripple on the v boost_x supply. dc - to - dc converter operation the on - board dc - to - dc converters use a constant frequency, peak current mode control scheme to step up an av cc input of 4.5 v to 5.5 v to drive the ad5735 output channel. these converters are designed to operate i n discontinuous conduction mode with a duty cycle of <90% typical. discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. the dc - to - d c converters are nonsync hronous ; that is, they require an external schottky diode. dc - to - dc converter output voltage when a channel current output is enabled, the converter regulates the v boost_x supply to 7.4 v (5%) or ( i out r load + he adroom), whichever is greater (see figure 51 for a plot of headroom supplied vs. output current). in voltage output mode with the output disabled, the converter regulates the v boost_x supply to 15 v (5%). in current output mode with the output disabled, the converter regulates the v boost_x supply to 7.4 v (5%). within a channel, the v out_x and i out_x stages share a common v boost_x supply ; therefore, the outputs of the i out_x and v out_x stages can be tied together (see the volt ag e and current output pins on the same terminal section) . dc - to - dc converter settling time i n current output mode, the settling time for a step greater than ~1 v (i out r load ) is dominated by the settling time of the dc - to - dc converter. the exception to t his is when the required voltage at the i out_x pin plus the compliance voltage is below 7.4 v (5%). figure 47 shows a typical plot of the output settling time. this plot is for a 1 k? load. the settling time for smaller loads is faster. the settling time for current steps less than 24 ma is also faster. dc - to - dc converter v max functionality the maximum v boost_x voltage is set in the dc - to - dc control register (23 v, 24.5 v, 27 v, or 29.5 v; see table 28) . when the maximum voltage is reached , the dc - to - dc converter is disabled, and the v boost_x volt age is allowed to decay by ~0.4 v. after the v boost_x voltage decay s by ~0.4 v, the dc - to - dc converter is reenabled, and the voltage ramps up aga in to v max , if still required. this operation is shown in figure 78 . 28.6 28.7 28.8 28.9 29.0 29.1 29.2 29.3 29.4 29.5 29.6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v boost_x vo lt age (mv) time (ms) v max 0m a t o 24m a range, 24m a output output unloaded dc-dc maxv bits = 29.5v dc-dcx bit dc-dcx bit = 0 dc-dcx bit = 1 f sw = 410khz t a = 25c 09961-183 figure 78 . operation on reaching v max as shown in figure 78 , the dc - dcx bit in the status register is assert ed when the ad5735 ramps up to the v max value but is deasserted when the voltage decays to v max ? ~0.4 v. dc - to - dc converter on - board switch the ad5735 contains a 0.425 ? internal switch. the switch cur rent is monitored on a pulse - by - pu lse basis and is limited to 0.8 a peak current. dc - to - dc converter sw itching frequency and phase the ad5735 dc - to - dc converter switching frequency can be selected from the dc - to - dc control register (see table 28) . the phasing of the chan nels can also be adjusted so that the dc - to - dc converter s can clock on different edges. for typical applications, a 410 khz frequency is recommended. at light loads (low output current and small load resistor), the dc - to - dc converter enters a pulse - skippin g mode to minimize switching power dissipation. dc - to - dc converter inductor selection for typical 4 ma to 20 ma applications, a 10 h inductor (such as the xal4040 - 103 from coi lcraft), combined with a switch ing frequency of 410 khz, allows up to 24 ma to b e driven into a load resistance of up to 1 k? with an av cc supply of 4.5 v to 5.5 v. it is important to ensure that the inductor can handle the peak current without saturating, especially at the maximum ambient temperature. if the inductor enters saturatio n mode, efficiency decreases . the inductance value also drops during saturation and may result in the dc - to - dc converter circuit not being able to supply the required output power.
data sheet ad5735 rev. b | page 43 of 48 dc - to - dc converter external schottky diode selection the ad5735 requires an external schottky diode for correct opera tion. ensure that the schottky diode is rated to handle the maximum reverse breakdown voltage expected in operation and that the maximum junction temperature of the dio de is not exceeded. the average current of the diode is approximately equal to the i load current. diodes with larger forward voltage drops result in a decrease in efficiency. dc - to - dc converter compensation capacitors because the dc - to - dc converter operate s in discontinuous conduc - tion mode , the uncompensated transfer function is essentially a single - pole transfer function. the pole frequency of the transfer function is determined by the output capacitance, input and output voltage, and output load of the dc - to - dc converter . the ad5735 uses an external capacitor in c onjunction with an internal 150 k? resistor to compensate the regulator loop. alternatively, an external compensation resistor can be used i n series with the compensation capacitor by setting the dc - dc c omp bit in the dc - to - dc control register (see table 28) . in this case, a resistor of ~50 k? is recommended. t he advantages of this configuration are described in the ai cc supply requirements slewing section. for typical applications, a 10 nf dc - to - dc com - pensation capacitor is recommended. dc - to - dc converter input and output capacitor selection the output capacitor affects the ripple voltage of the dc - to - dc converter and indirectly limits the maximum slew rate at which the channel output current can rise. the ripple voltage is caused by a combination of the capacitance and the equivalent series resistance (esr) of the capacitor. for typical appl ications , a ceramic capacitor of 4.7 f is recommended . larger capacitors or parallel capacitors improve the ripple at the expense of reduced slew rate. larger capacitors also affect the current requirements of the a v cc suppl y while slewing (see the ai cc supply requirements slewing section ). the capacitance at the output of the dc - to - dc converter should be >3 f under all operating conditions. the input capacitor provides much of the dynamic current required for the dc - to - dc conve rter and should be a low esr component. for the ad5735 , a lo w esr tantalum or ceramic capacitor of 10 f is recommended for typical applications. ceramic capacitors must be chosen carefully because they can exh ibit a large sensitivity to dc bias voltages and temperature. x5r or x7r dielectrics are preferred because these capacitors remain stable over wider operating voltage and temperature ranges. care must be taken if selecting a tantalum capacitor to ensure a low esr value. ai cc supply requirements static the dc - to - dc converter is designed to supply a v boost _x voltage of v boos t_x = i out r load + headroom (2) see figure 51 for a plot of headroom supplied vs. output c urrent . therefore , for a fixed load and output voltage, the output current of the dc - to - dc converter can be calculated by the following formula: cc v boost out cc cc av v i av efficiency out power ai boost = = (3) where: i out is the output current from i out_x in amp ere s. v boost is the efficiency at v boost_x as a fraction (see figure 53 and figure 54). ai cc supply requirements slewing the ai cc current requirement while slewing is greater than in static operation because the output power increases to charge the output capacitance of the dc - to - dc converter. this transient current can be quite large (see figure 79 ), although the methods described in the reducing ai cc current requirements section can reduce the requirements on the av cc supply. if not enough ai cc current can be provided, the av cc voltage drops. due to this av cc drop, the ai cc current required for slew ing incre ases further , causing the voltage at av cc to drop further (see equation 3) . in this case, the v boost _x voltage and , therefore, the output voltage, may never reach their intended value s . because th e av cc voltage is common to all channels, this voltage drop may also affect other channels. 0 5 10 15 20 25 30 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.5 1.0 1.5 2.0 2.5 i out_x current (m a)/ v boost_x vo lt age (v) ai cc current (a) time (ms) ai cc i out v boost 0m a t o 24m a range n?/2$' f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 09961-184 figure 79 . ai cc current vs. time for 24 ma s tep through 1 k load with internal compensation resistor
ad5735 data sheet rev. b | page 44 of 48 reducing ai cc current requirements two main methods can be used to reduce the ai cc current requirements. one method is to add an external compensation resistor, and the other is to use slew rate c ontrol. these methods can be used together. adding an external compensation resistor a compensation resistor can be placed at the comp dcdc_x pin in series with the 10 nf compensation capacitor. a 51 k? exter - nal compensation resistor is recommended. this c ompensation increases the slew time of the current output but reduces the ai cc transient current requirements. figure 80 shows a plot of ai cc current for a 24 ma step through a 1 k? load when using a 51 k? compens ation resistor. the compensation resistor reduces the current requirements through smaller loads even further, as shown in figure 81. 0 4 12 8 16 24 20 28 32 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ai cc current (a) 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 0 0.5 1.0 1.5 2.0 2.5 i out_x current (m a)/ v boost_x vo lt age (v) time (ms) ai cc i out v boost 09961-185 figure 80 . ai cc current vs. time for 24 ma step thro ugh 1 k? load with external 51 k? compensation resistor 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ai cc current (a) 0m a t o 24m a range 500? load f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 0 4 12 8 16 24 20 28 32 0 0.5 1.0 1.5 2.0 2.5 i out_x current (ma)/v boost_x vo lt age (v) time (ms) ai cc i out v boost 09961-186 figure 81 . ai cc current vs. time for 24 ma step through 500 ? load with external 51 k? compensation resistor using slew rate control using slew rate control can greatly r educe the current require - ments of t he av cc supply , as shown in figure 82. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ai cc current (a) 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 0 4 12 8 16 24 20 28 32 0 1 2 3 4 5 6 i out_x current (m a)/ v boost_x vo lt age (v) time (ms) ai cc i out v boost 09961-187 figure 82 . ai cc current vs. time for 24 ma step through 1 k? load with slew rate control when using slew rate control, it is important to remember that the output cannot slew faster than the dc - to - dc converter. the dc - to - dc converter slews slowest at higher currents through large loads (for example, 1 k?). the slew rate is also dependent on the configuration of t he dc - to - dc converter . two examples of the dc - to - dc converter output slew are shown in figure 80 and figure 81. (v boost corresponds to the output voltage of the dc - to - dc converter.)
data sheet ad5735 rev. b | page 45 of 48 applications informa tion voltage and current output pins on the same terminal when using a channel of the ad5735 , the current and voltage output pins can be connected to two separate terminal s or tied together and connected to a single terminal. the t wo output pins can be tied together because only the voltage output or the current output can be enabled at any one time. when the current output is enabled, the voltage output is in tristate mode , and when the voltage output is enabled, the current output is in tristate mode. when the two output pins are tied together , the poc pin must be tied low and the poc bit in the main control register set to 0, or, if the poc pin is tied high, the poc bit i n the main control register must be set to 1 before the current output is enabled. as shown in the absolute maximum ratings section, the output tolerances are the same for both the voltage and current output pins. the +v sense_x and ?v sense_x connections are buffered so that current leakage into these pins is negligible when the part is operated in current output mode. current output mode with internal r set when using the internal r set resistor in current output mode, the output is significantly affected by how many other channels using the internal r set are enabled and by the dc crosstalk from these channels. the internal r set specifications in table 1 are for all four channels enabled with the internal r set selected and outputting the same code. for every channel enabled with the internal r set , the offset error decreases. for example, with one current output enabled using the internal r set , the offset error is 0.075% fsr. this value de creases proportionally as more current channels are enabled; the offset error is 0.056% fsr on each of two channels, 0.029% fsr on each of three channels, and 0.01% fsr on each of four channels. similarly, the dc crosstalk when using the internal r set is p ropor - tional to the number of current output channels enabled with the internal r set . for example, with the measured channel at 0x8000 and another channel going from zero to full scale, the dc crosstalk is ?0.011% fsr. with two other channels going from zero to full scale, the dc crosstalk is ?0.019% fsr, and with all three other channels going from zero to full scale, it is ?0.025% fsr. for the full - scale error measurement in table 1 , all channels are at 0xffff. this means that as any channel goes to zero scale, the full - scale error increases due to the dc crosstalk. for example, with the measured channel at 0xffff and three channels at zero scale, the full - scale error is 0.025% fsr . similarly, if only one channel is enabled in current output mode with the internal r set , the full - scale error is 0.025% fsr + 0.075% fsr = 0.1% fsr. precision voltage re ference selection to achieve the optimum performance from the ad5735 over its full operating temperature range, a precision voltage reference must be used. care should be taken with the selection of the precision voltage reference. the voltage applied to the reference inputs is used to provide a buffered reference for the dac cores. therefore, any error in the voltage reference is reflected in the outputs of the ad5735 . f our possible sources of error must be consider ed when choosi ng a voltage reference for high accuracy applications: initial accuracy, long - term drift, temperature coefficient of the output voltage , and output voltage noise. initial accuracy error on the outp ut voltage of an external ref - er ence can lead to a full - sca le error in the dac. therefore, to minimize these errors, a reference with a low initial accuracy error specification is preferred. choosing a reference with an output trim adjustment, such as the adr435 , allows a system designer to trim out system errors by setting the reference voltage to a voltage other than the nominal. the trim adjust - ment can be used at any temperature to trim out any error. long - term drift is a measure of how much the reference output volta ge drifts over time. a reference with a tight long - term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. the temperature coefficient of the reference output voltage affects inl, dnl, and tue. a refer ence with a tight temperature coef - ficient specification should be chosen to reduce the dependence of the dac output voltage on ambient temperature. in high accuracy applications, which have a relatively low noise budget, reference output voltage noise mus t be considered. choos - ing a reference with as low an output noise voltage as practical for the system resolution required is important. precision voltage references such as the adr435 (xfet ? design) produce lo w output noise in the 0.1 hz to 10 hz bandwidth . however, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. table 37 . recommended precision voltage references p art no. initial accuracy (mv maximum) long - term drift (ppm typical) temperature coefficient (ppm/c maximum) 0.1 hz to 10 hz noise (v p - p typical) adr445 2 50 3 2.25 adr02 3 50 3 10 adr435 2 40 3 8 adr395 5 50 9 8 AD586 2.5 15 10 4
ad5735 data sheet rev. b | page 46 of 48 driving inductive lo ads when drivi ng inductive or poorly defined loads, a capacitor may be required between the i out_x pin and the agnd pin to ensure stability. a 0.01 f capacitor between i out_x and agnd ensures stability of a load of 50 mh. the capacitive component of the load may cause slower settling, althoug h this may be masked by the set tling time of the ad5735 . there is no maxi - mum capacitance limit for the current output of the ad5735 . transi ent voltage protecti on the ad5735 contains esd protection diodes that prevent dam - age from normal handling. the industrial control environment can, however, subject i/o circuits to much higher transients. to pr otect the ad5735 from excessively high voltage transients, external power diodes and a surge current limiting resistor (r p ) are required, as shown in figure 83 . a typi cal value for r p is 10 ?. the two protection diodes and the resistor (r p ) must have appro - priate power ratings. r load r d1 d2 p ad5735 v boost_x i out_x agnd 09961-079 c d c d c 4 . 7 f c f i l t e r 0 . 1 f r f i l t e r 1 0 ? (from dc- t o-dc converter) figure 83 . output transient voltage protection further protection can be provided using transient voltage suppressors (tvs s ), also referred to as transorbs. these compo - nents are available as unidirectional suppressors, which protect against positive high voltage transients, and as bidirectional suppressors, which protect against both positive and negative high voltage transients. transient vo ltage suppressors are avail - able in a wide range of standoff and breakdown voltage ratings. the tvs should be sized with the lowest breakdown voltage possible while not conducting in the functional range of the current output. it is recommended that all fi eld connected nodes be protected. the voltage output node can be protected with a similar circuit, where d2 and the transorb ar e connected to av ss . f or the volt - age output node, the +v sense_x pin should also be protected with a large value series resistanc e to the transorb, such as 5 k?. in this way, the i out_x and v out_x pins can also be tied together and share the same protection circuitry. microprocessor inter facing microprocessor interfacing to the ad5735 is via a serial bus that uses a protocol compatible with microcontrollers and dsp processors. the communication channel is a 3 - wire minimum interface consisting of a clock signal, a data signal, and a latch signal. the ad5735 requires a 24 - bit data - word with data valid on the falling edge of sclk. the dac output update is initiated either on the rising edge of ldac or, if ldac is held low, on the rising edge of sync . the contents of the registers can be read using the readback function. ad5735 - to - adsp - bf527 interface the ad5735 can be connected directly to the sport interface of the adsp - bf527 , an analog devices, inc., blackfin? dsp. figure 84 shows how the sport interface can be connected to control the ad5735 . ad5735 sync sclk sdin ldac sport_tfs sport_tsclk sport_dt0 gpio0 adsp-bf527 09961-080 figure 84 . ad5735 - to - adsp - bf527 sport interface layout guidelines grounding in any circuit where accuracy is important, careful consider - ation of the power supply and ground return layout helps to ensure the rated performance. t he printed circuit board on which the ad5735 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5735 is in a system where multiple devices require an agnd - to - dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the gndsw x pin and the ground connection for the av cc supply are referred to as pgnd. pgnd should be confined to certain areas of the board, and the pgnd - to - agnd connection should be made at one point only. supply decoupling the ad5735 shou ld have ample supply bypassing of 10 f in parallel with 0.1 f on each supply , located as close to the package as possible, ideally right up against the device. the 10 f capac - itors are the tantalum bead type. the 0.1 f capacitor s should have low effect ive series resistance (esr) and low effective series inductance (esl), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents d ue to internal logic switching.
data sheet ad5735 rev. b | page 47 of 48 traces the power supply lines of the ad5735 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded w ith digital ground to prevent radi - ating noise to other parts of the board and should never be run near the reference inputs. a ground line routed between the sdin and sclk trac es helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separating the lines helps). it is essential to minimize noise on the refin line because it couples through to the dac output. avoid crossover of digital and analog signals. traces on oppo - site sides of the board should ru n at right angles to each other to reduce the effects of feedthrough on the board. a microstrip technique is by far the best method, but i t i s not always possible with a double - sided board. in this technique, the component side of the board is dedicated t o ground plane, and signal traces are placed on the solder side. dc - to - dc converters to achieve high efficiency, good regulation, and stability, a well - designed printed circuit board layout is required. follow these guidelines when designing printed circu it boards (see figure 77): ? keep the low esr input capacitor, c in , close to av cc and pgnd. ? keep the high current path from c in through the inductor ( l dcdc ) to sw x and pgnd as short as possible. ? keep the high curren t path from c in through the inductor (l dcdc ) , the diode ( d dcdc ), and the output capacitor ( c dcdc ) as short as possible. ? keep high current traces as short and as wide as possible. the path from c in through the inductor (l dcdc ) to sw x and pgnd should be able to handle a minimum of 1 a. ? place the compensation components as close as possible to the comp dcdc_x pin. ? avoid routing high impedance traces near any node connected to sw x or near the inductor to prevent radiated noise injection. galvanically isolate d in terface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common - mode voltages that may occur. the analog devices i coupler ? product s can provide voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5735 makes it ideal for isolated interfaces because the number of inter - face lines is k ept to a minimum. figure 85 shows a 4 - channel isolated interface to the ad5735 using an adum1411 . for more information, vi sit www.analog.com . v ia seria l clock out t o sclk v oa encode decode v ib seria l d at a out t o sdin v ob encode decode v ic sync out v oc encode decode v id contro l out v od encode decode microcontroller adum14 1 1 t o sync t o ldac 09961-081 figure 85 . 4 - channel isolated interface to the ad57 3 5
ad5735 data sheet rev. b | page 48 of 48 outline dimensions compliant to jedec standards mo-220-vmmd-4 080108-c 0.25 min top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 ty p 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) sea ting plane pin 1 indic at or 7.25 7.10 sq 6.95 pin 1 indic at or 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 86 . 64 - lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp - 64 - 3) dimensions shown in millimeters ordering guide model 1 resolution (bits) temperature range package description package option ad5735 acpz 12 ?40c to +105c 64 - l ead lfcsp_vq cp - 64 - 3 ad5735acpz- reel7 12 ?40c to +105c 64-l ead lfcsp_vq cp-64-3 1 z = rohs compliant part. ? 2011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09961 -0- 5/12(b)

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